• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.2
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• pp.112-119
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• 2009

This paper presents a PLL(Phase Lock Loop) approach for effective speed and torque control of high speed miniature BLDCM(Brushless DC Motor) using hall sensor. The proposed speed control method based on PLL uses only a phase shift between reference pulse signal according to speed reference and actual pulse signal from hall sensor. It doesn't use any speed calculation, and calculates a direct current reference from phase shift. The current reference is changed to reduce the phase shift between reference and actual pulse. So the actual speed can keep the reference speed. The proposed control scheme is very simple but effective speed control is possible. In order to obtain a smooth torque production, the reference current is changed using acceleration and deceleration slope. The proposed control scheme is verified by experimental results of the 50W, 40,000[rpm] high speed miniature BLDCM.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.6
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• pp.286-295
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• 2006

This paper presents a design of a real-time software GPS receiver which runs on a PC. The software GPS receiver has advantages over conventional hardware based receivers in terms of flexibility and efficiency in application oriented system design and modification. In odor to reduce the processing time of the software operations in the receiver, a shared memory structure is used with a dynamic data control, and the byte-type IF data is processed through an Open Multi-Processing technique in the mixer and integrator which requires the most computational load. A high speed data acquisition device is used to capture the incoming high-rate IF signals. The FFT-IFFT correlation technique is used for initial acquisition and FLL assisted PLL is used for carrier tracking. All software modules are operated in sequence and are synchronized with pre-defined time scheduling. The performance of the designed software GPS receiver is evaluated by running it in real-time using the real GPS signals.

• Proceedings of the KIEE Conference
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• 2008.10c
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• pp.132-135
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• 2008

This paper presents a PLL(Phase Lock Loop) control method for speed control of high speed miniature BLDCM(Brushless DC Motor) using hall sensor. The Proposed PLL based speed control method uses a only phase shift between reference pulse signal according to speed reference and actual pulse signal from hall sensor. It doesn't use any speed calculation, and calculates a direct current reference from phase shift. The current reference is changed to reduce the phase shift between reference and actual pulse. So the actual speed can keep the reference speed. The proposed control scheme is very simple but effective speed control is possible.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2350-2352
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• 2004

This paper presents the implementation-tation of the real-time software GPS Receiver based on FFT and FLL assisted PLL tracking algorithm. The FFT(fast fourier transform) based GPS si-gnal acquisition scheme provides a fast TTFF(time to first fix) performance. The tracking based on FLL assisted PLL enables tracking of GPS signal in a high dynamic environment. The designed software GPS receiver uses the indexing method for generating replica carrier to reduce computation load. The performance of the implemented GPS receiver is evaluated using high-dynamic simulated data from a simulator and real static data.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.31-39
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• 2012

In this paper, we propose a microprocessor-based automatic voltage regulator(AVR) to reduce consumers' electric energy consumption and to help controlling peak demanding power. Hybrid Switching Automatic Voltage Regulator (HS-AVR) consist of a toroidal core, several tap control switches, display and command control parts. The coil forms an autotransformer which has a serial main winding and four parallel auxiliary windings. It controls the output voltage by changing the combination of the coils and the switches. Relays are adopted as the link switches of the coils to minimize the loss. To make connecting and disconnecting time accurate, relays of the circuit have parallel TRIACs. A software phase locked loop(PLL) has been used to synchronize the timings of the switches to the voltage waveform. The software PLL informs the input voltage zero-crossing and positive/negative peak timing. The traditional voltage transformers and AVRs have a disadvantage of having a large mandatory capacity to accommodate maximum inrush current to avoid the switch contact damage. But we propose a suitable AVR for every purpose in smart grid with reduced size and increased efficiency.

• Journal of Advanced Marine Engineering and Technology
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• v.17 no.3
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• pp.60-69
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• 1993

The speed control associated with dc servo motors for direct-drive applications of mobile robot is considered in this study. Robot is moved by power wheeled steering of two dc servo motors mounted to it. In order to cooperate with micro-computer and to achieve the high-performance operation of dc servo motor, speed control system is composed of a digital Phase Locked Loop and H-type drive circuit. And the motor is driven by Pulse Width Modulations. In controlling PWM, it is modified to compose of H-type drive circuit with feedback diodes and switching transistor and design of control sequence so that it may show linear characteristics. As a result, speed characteristics of motor showed linear features. In order to get data on design of PLL control system, the parameters of 80[W[ motor & robot device is measured by simple software control. The PLL speed control system is schemed and designed by leaner drive circuit and measured parameters. A complete speed control system applied to 80[W] dc servo motor showed good linearity, stability and high response. Also, it is verified that the PLL speed control system has good compatibility as a mobile robot driver.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.07a
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• pp.47-50
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• 2012

본 연구에서는 수용가에서 에너지 절감과 최대수요전력 제어를 위하여 마이크로프로세서를 이용한 고효율 자동 전압 조정기의 제어 방법에 대하여 제안한다. 제안한 고효율 자동 전압 조정기는 트로이달 코아에 1개의 직렬 권선과 분리된 4개의 분로 권선으로 구성되어 있는 단권 변압기를 사용한다. 변압기의 전압 조정은 직렬 권선과 분로 권선의 연결 방법에 따라 감압/승압이 가능하다. 스위치는 릴레이와 트라이악을 병행하여 사용한다. 스위치의 조작 시 발생하는 권선의 여자돌입전류를 제어하기 위하여 트라이악을 이용 연결 상태를 변경하고 연결 상태 유지 시에는 릴레이를 이용함으로써 스위치 소비 전력을 최소화 한다. 제어신호는 여자 돌입 전류를 줄이기 위하여 전압 파형에 동기화 하여 제어되며 이를 위하여 소프트웨어 PLL을 사용한다. 소프트웨어 PLL은 전압 파형의 zero-cross, 전압 최고점 등의 시간을 생성한다. 권선 스위치의 제어, 소프트웨어 PLL등 자동 전압 조정기의 제어는 마이크로프로세서에 의해서 이루어진다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.235-240
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• 2006

Ionospheric scintillation induces a rapid change in the amplitude and phase of radio wave signals. This is due to irregularities of electron density in the F-region of the ionosphere. It reduces the accuracy of both pseudorange and carrier phase measurements in GPS/satellite based Augmentation system (SBAS) receivers, and can cause loss of lock on the satellite signal. Scintillation is not as strong at mid-latitude regions such that positioning is not affected as much. Severe effects of scintillation occur mainly in a band approximately 20 degrees on either side of the magnetic equator and sometimes in the polar and auroral regions. Most scintillation occurs for a few hours after sunset during the peak years of the solar cycle. This paper focuses on estimation of the effects of ionospheric scintillation on GPS and SBAS signals using a software receiver. Software receivers have the advantage of flexibility over conventional receivers in examining performance. PC based receivers are especially effective in studying errors such as multipath and ionospheric scintillation. This is because it is possible to analyze IF signal data stored in host PC by the various processing algorithms. A L1 C/A software GPS receiver was developed consisting of a RF front-end module and a signal processing program on the PC. The RF front-end module consists of a down converter and a general purpose device for acquiring data. The signal processing program written in MATLAB implements signal acquisition, tracking, and pseudorange measurements. The receiver achieves standalone positioning with accuracy between 5 and 10 meters in 2drms. Typical phase locked loop (PLL) designs of GPS/SBAS receivers enable them to handle moderate amounts of scintillation. So the effects of ionospheric scintillation was estimated on the performance of GPS L1 C/A and SBAS receivers in terms of degradation of PLL accuracy considering the effect of various noise sources such as thermal noise jitter, ionospheric phase jitter and dynamic stress error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.