• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.961-962
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• 2006

The AMBA(Advanced Microcontroller Bus Architecture) system is one of the most important elements having an influence upon system performance in ARM-based SoC environments. The system guarantees easy connection and good performance as a 32-bit bus system for ARM processors. In this paper, we analyze arbitration algorithms for the AHB bus of the AMBA system and propose an efficient algorithm to improve the performance of the bus system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.780-783
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• 2012

Recently, the SoC industry mainly uses various multi-layered bus architectures. However, reckless use of bus layers may results in on-chip communication resources and waste of silicon area. This paper performs a quantitative analysis to compare the two de-facto on-chip buses and SNP. Through the performance estimation, the performance of SNP turns out to be significantly enhanced for asymmetric write and read traffic (non-central F distribution) while symmetric traffic is similar to that of AXI. More specifically, SNP properly places IP cores on the top or bottom, induces the write and read channels to be balanced, and achieves about twenty percent improved performance compared to AXI.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.5
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• pp.1-7
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• 2008

The general bus architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. Specially, as several masters do not concurrently receive the right of bus usage, the arbiter plays an important role in arbitrating between shared bus and masters. Fixed priority, round-robin, TDMA and Lottery methods are developed in general arbitration policies, which lead the efficiency of bus usage in shared bus. On the other hand, the bus architecture can be modified to maximize the system performance. In the paper, we propose the flying master bus architecture that supports the parallel bus communication and analyze its merits and demerits following various arbitration policies that are mentioned above, compared with normal shared bus. From the results of performance verification using TLM(Transaction Level Model), we find that more than 40% of the data communication performance improves, regardless of arbitration policies. As the flying master bus architecture advances its studies and applies various SoCs, it becomes the leading candidate of the high performance bus architecture.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.569-570
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• 2008

This paper proposed a new arbitration method in arbiter which is one of bus system components for the design of SoC. Considering compatibility between IP and bus system, the performance of bus system can change the performance of SoC chip. The proposed arbitration method achieved the performance improvement with high efficiency depending on the environment in use.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.15-21
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• 2008

Several shared buses are divided hierarchically and connected with a bridge in the bus topology that consists of many components such as SoCs. Because the bridge topology is capable of the simultaneous communication of components in the several buses, the bus performance has improved definitely. However, when the inter-bus data transaction happens, the latency increases seriously in the bridge block. In this paper, a variety of bridge architectures are analyzed in the point of view of merit and demerit. Superior frying bridge topology is proposed in the aspects of performance, IP reusability, timing margin, gate count and circuit complexity. In contrast with the conventional bridge that has only a role to switch the inter-bus data, the frying bridge can communicate directly between the bus and the slave, which decreases the traffic overhead of a shared bus and improves the performance of a bridge communication.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2261-2266
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.