• IT SoC Magazine
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• s.19
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• pp.24-28
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• 2007

올해 44회를 맞이한 DAC(Design Automation Conference)는 6월 4일부터 8일까지 5일간 캘리포니아 샌디에고에서 개최되었다. 이번 DAC에도 샌프란시스코에서 열렸던 43회 DAC와 마찬가지로 인텔, IBM, ARM, Sun Microsystems 등 첨단 SoC/IP 설계회사와 Cadence, Synopsys 등 EDA 개발회사, 그리고 TSMC, UMC 등 유수의 파운드리회사들이 참가하였다. 전시회 참여업체는 약 250여개로 예년보다 약간 증가하였고 총 참관객수는 11,000여명으로 다소 줄어들었다. 하지만 국내 참여업체 관계자들은 참관객들의 질적인 수준이 작년 DAC보다 더 높아 제품을 홍보하고 관련 업계 사람들과 정보를 교환하기에 더없이 좋은 기회였다고 평가했다. 또한 이번 DAC 컨퍼런스는 총 10개 트랙, 53개의 세션들이 진행되었으며 약 161개의 논문이 발표되어 매우 역동적인 기술교류가 이루어졌다. 여기에서는 44th DAC의 주요 이슈와 전시회에 참여하였던 국내 SoC업체들의 제품에 대해 살펴 보고자한다.

• The Magazine of the IEIE
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• v.30 no.9
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• pp.1002-1011
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• 2003

In this paper, we introduce an integrated SoC front-end design & verification environment which can be practically used in the embedded 32-bit processor-core SoC VLSI design. Our introduced SoC design & verification environment integrates two most important flows, such as the RTL power estimation and code coverage analysis, with the functional verification (chip validation) flow which is used in the conventional simulation-based design. For this, we developed two simulation-based inhouse tools, RTL power estimator and code coverage analyzer, and used them to adopt them to our RTL design and to increase the design quality of that. Our integrated design environment also includes basic design and verification flows such as the gate-level functional verification with back annotation information and test vector capture & replay environment.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.667-668
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• 2006

Radio Frequency Identification (RFID) is an automatic identification method, relying on storing and remotely retrieving data using devices called RFID tags or transponders. RFID systems is coming into increasing use in industry and logistics. This paper discuses implementation of multi-protocol RFID reader SoC. The SoC contains multi-protocol RFID RFID reader, CPU, UART, memory.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.1
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• pp.156-160
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• 2011

This paper describes the design and implementation of a System-on-a-Chip (SoC) for pattern recognition to use in embedded applications. The target Soc consists of LEON2 core, AMBA/APB bus-systems and custom-designed accelerators for Gaussian Pyramid construction, lighting compensation and histogram equalization. A new FPGA-based prototyping platform is implemented and used for design and verification of the target SoC. To ensure that the implemented SoC satisfies the required performances, a pattern recognition application is performed.

• Electronics and Telecommunications Trends
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• v.23 no.6
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• pp.92-101
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• 2008

전원관리 및 전력소모 절감 기술은 휴대폰, 노트북 등의 휴대 기기 사용이 보편화되고 다기능화, 고성능화함에 따라 지속적으로 발전해 왔다. 특히 반도체 소자의 선폭이 나노미터급으로 초미세화 됨에 따라 누설 전류가 급증하고 칩의 처리 성능을 높이기 위해 클록 주파수를 높이면서 스위칭 전류 소모도 증가하므로, 이러한 동적/정적 전력소모 증가를 억제시킬 수 있는 다중 문턱전압 소자, DVFS, sub-threshold, 클록 게이팅, 저전압 회로 기술이 SoC 설계에 점진적으로 적용되고 있다. 이에 본 고에서는 휴대폰용 부품을 중심으로, 무선 통신 기능을 갖춘 기기의 전력소모 요인을 분석하고 배터리 사용시간을 연장시킬 수 있는 저전력 SoC 기술 동향을 살펴보고자 한다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.135-138
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• 2005

HDL(Hardware Description Language) is the most important modem tools used to describe hardware, and becomes important as we move to higher levels of abstraction. The HDL has been made brisk use of in analog design, MEMS device[1-2], process related field as well as digital design. The most important characteristics of HDL is Abstraction which is the strongest tool that extend greatly designer's design ability. In this paper by the Modelling Continuum with hierarchical structure of abstraction, we apply UML(Unified Modeling Language) to SoC Design with HDL UML makes an easy and visual description of the various levels of abstraction, and gives designers good flexible modeling capabilty for SoC Design.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.11a
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• pp.55-56
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• 2009

내장형 프로세서에 대한 기능요구사항이 날로 증가함에 따라 데이터 처리량을 늘리기 위한 많은 연구들이 지속되어 왔으며, 그중 파이프라인의 컨트롤 해저드로 인한 성능저하를 최소화하기 위한 분기 예측 기법이 다양한 방식으로 제안되어 왔다. 본 논문에서는 분기예측 방법으로서 구현이 간단하고 분기 예측률이 높은 BTB 방식을 32비트 프로세서에 적용하고, 해당 프로세서를 사용하는 SoC 플랫폼을 구성하여 분기예측기법 사용으로 인한 성능향상을 측정하고, 0.18um ASIC 공정을 적용하여 SoC 플랫폼을 구현한 결과를 제시한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.109-114
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• 2010

In this paper, the implementation of a human signal sensing module that has capabilities to check and restore the weak signals from the human body is presented. A module presented in this paper consists of processing and sensing elements related to human pulse and body temperature and a controller implemented with SoC design method. PPG data is detected by a noise filtering process toward the amplified signal which is from the operating frequency between 0.1Hz - 10Hz. A digital temperature sensor is used to check the body temperature. A sensor outputs the corresponding value of the electric voltage according to the body temperature. Moreover, this paper discusses the implementation of an enhanced microprocessor which is synthesized with VHDL as a part of the SoC development and used to control the entire module. The SoC processor is implemented on a Xilinx Spartan 3 XC3S1000 device and has the achieved operating frequency of 10MHz. The implemented SoC processor core is successfully tested with macro memories in FPGA and the experimental results are hereby shown.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• Journal of IKEEE
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• v.23 no.2
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• pp.388-394
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• 2019

This paper describes a design of security system-on-chip (SoC) that integrates a Cortex-M0 CPU with an AAW (ARIA-AES- Whirlpool) crypto-core which implements two block cipher algorithms of ARIA and AES and a hash function Whirlpool into an unified hardware architecture. The AAW crypto-core was implemented in a small area through hardware sharing based on algorithmic characteristics of ARIA, AES and Whirlpool, and it supports key sizes of 128-bit and 256-bit. The designed security SoC was implemented on FPGA device and verified by hardware-software co-operation. The AAW crypto-core occupied 5,911 slices, and the AHB_Slave including the AAW crypto-core was implemented with 6,366 slices. The maximum clock frequency of the AHB_Slave was estimated at 36 MHz, the estimated throughputs of the ARIA-128 and the AES-128 was 83 Mbps and 78 Mbps respectively, and the throughput of the Whirlpool hash function of 512-bit block was 156 Mbps.