• Proceedings of the KAIS Fall Conference
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• 2009.05a
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• pp.255-258
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• 2009

최근 EDA 툴의 기술적인 향상과 반도체 공정의 발달로 IC 설계자들은 RISC 프로세서, DSP 프로세서, 메모리 등 많은 IP가 하나로 집적되는 SoC구조가 가능해졌다. 하지만 기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가진다. 이러한 문제점은 SoC 내부의 IP들이 많을수록 SoC 플랫폼의 전체 성능이 저하되어, CPU 자체의 속도보다는 효율적인 통신에 의해 성능이 좌우된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 성능을 향상시키기 위하여 크로스바 스위치버스 구조를 제안한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스 구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상됨을 확인하였다.

• Journal of IKEEE
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• v.13 no.2
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• pp.101-107
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• 2009

Growth in the VLSI process and design technology is resulting into a continuous increase in the number of IPs on a chip to form a system. Because of many IPs on a single chip, efficient communication between IPs is essential. We propose a dynamically reconfigurable 3-layer bus structure which can adapt to the pattern of data transmission to achieve an efficient data communication between various IPs. The proposed 3-layer bus can be reconfigured to multi-single bus mode, and single-multi bus mode, thus providing the benefits of both single-bus and multi-bus modes. Experimental results show that the flexibility of the proposed bus structure can reduce data transmission time compared to the conventional fixed bus structure. We incorporated the proposed bus structure in a JPEG system and verified that the proposed structure achieved an average of 22% improvement in time over the conventional fixed bus structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.35-44
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• 2005

SoC(systnn-on-a-chip) requires high bandwidth system bus for performing multiple functions. Performance of the system is affected by bandwidth of the system bus. In this paper, for efficient management of the bus resource on a SoC platform, we present a latency model of the shared bus organized by multiple layers. Using the latency model, we can analyze latencies of the shared bus on a SoC. Moreover we evaluate a throughput of the bus and compare with needed throughput of the SoC platform including IPs such as MPEG or USB 2.0. And we can use the results as a criteria to find out an optimal bus architecture for the specific SoC design. For verifying accuracy of the proposed model, we compared the latencies with the simulation result from MaxSim tools. As the result of simulation, the accuracy of the IS model for a single layer and multiple layer are over $96\%\;and\;85\%$ respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.780-783
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• 2012

Recently, the SoC industry mainly uses various multi-layered bus architectures. However, reckless use of bus layers may results in on-chip communication resources and waste of silicon area. This paper performs a quantitative analysis to compare the two de-facto on-chip buses and SNP. Through the performance estimation, the performance of SNP turns out to be significantly enhanced for asymmetric write and read traffic (non-central F distribution) while symmetric traffic is similar to that of AXI. More specifically, SNP properly places IP cores on the top or bottom, induces the write and read channels to be balanced, and achieves about twenty percent improved performance compared to AXI.

• The Journal of the Korea Contents Association
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• v.7 no.11
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• pp.84-93
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• 2007

This paper presents a methodology that accelerates estimating the system-level power consumption for on-chip bus of SoC platforms. The proposed power modeling can estimate the power consumption according to the change of a target SoC system. The proposed model comprises two parts: the one is power estimation of bus logics reflecting the architecture of the bus such as the number of bus layers, the other is to estimate the power consumed by the bus lines during data transmission. We designed the target multimedia SoC system, MPEG encoder as an example and evaluated power consumption using this model. The simulation result shows that the accuracy of the proposed model is over 92%. Thus, the proposed power model can be used to design of a high-performance/low-power multimedia SoC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.65-72
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• 2005

We can integrate more IP blocks on a silicon die as the development of fabrication technologies and EDA tools. Consequently, we can design complicated SoC architecture including multi-processors. However, most of existing SoC buses have bottleneck in on-chip communication because of shared bus architectures, which result in the performance degradation of systems. In most cases, the performance of a multi-processor system is determined by efficient on-chip communication and the well-balanced distribution of computation rather than the performance of the processors. We propose an efficient SoC Network Architecture(SNA) using crossbar routers which provide a solution to ensure enough communication bandwidth. The SNA can significantly reduce the bottleneck of on-chip communication by providing multi-channels for multi-masters. According to the proposed architecture, we design a model system for the SNA. The proposed architecture has a better efficiency by $40\%$ than the AMBA AHB according to a simulation result.