• Journal of the Korean Society of Safety
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• v.12 no.4
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• pp.3-8
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• 1997

This paper shows a performance estimation of windowing a single tone with added Gaussian noise and uniform noise. Signal-to-noise ratio can be determined by the ratio of the output noisy signal variance to the input noisy signal variance of a window. Standard deviation of noise is reduced by windowing Signal-to-noise ratio of the noisy signal is reduced by the windowing operation. Thus, performance of window function can be determined by this filtering operation that improved the signal-to-noise ratio.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.5
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• pp.38-43
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• 1996

Windowing routines have as their purpose the reduction of the sidelobes of a spectral output of the FFT or DFT routines. Windowing routines accomplish this by forcing the beginning and end of any sequence to approach each other in value. Since they must work with any sequence they force the beginning and ending samples near zero. To make up for this reduction in power, windowing routines give extra weight to the values near the middle of the sequence. The difference between windows is the way in which they transition from the low weights near the edges to the higher weights neqr the middle of the sequence. Signal-to-noise ratio(SNR) can be determined by the ratio of the output noisy signal variance to the input noisy signal variance of a window. Standard deviation of noise is reduced by windowing. Thus, the windowing operation improved the SNR of the noisy signal. This paper shows a performance estimation of windowing on a single tone with added Gaussian noise and uniform noise.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.4-7
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• 1997

When we use Hadamard transform spectrometers (HTS), we can increase signal to noise ratio(SNR) by multiplexing which is done by masks. But if the mask has a single defective element, output-SNR decreases. In this paper the effect of a single defective element on the output-SNR is investigated. And a method of compensating for the defective mask element is presented.

• Speech Sciences
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• v.8 no.2
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• pp.73-81
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• 2001

In this paper, we focus on the real time implementation of the single channel adaptive noise canceller(ANC) by using TMS320C30 EVM board. The implemented single channel adaptive noise canceller is based on a reference paper [1] in which it is simulated by using the recursive average magnitude difference function(AMDF) to get a properly delayed input speech on a sample basis as a reference signal and normalized least mean square(NLMS) algorithm. To certify results of the real time implementation, we measured the processing time of the ANC and enhancement ratio according to various signalto-noise ratios(SNRs). Experimental results demonstrate that the processing time of the speech signal of 32ms length with delay estimation of every 10 samples is about 26.3 ms, and almost the same performance as given in [1] is obtained with the implemented system.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1984.10a
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• pp.53-56
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• 1984

This paper shows that the error probabilities for coherent and noncoherent BF나 systems combined with FH in the presence of single channel tone interference. The performance is developed as functions of the signal to noise ratio and jamming to noise ratio. A specific results for two phases of ㅠ/4 and ㅠ/2 is obtained.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1920-1923
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• 2002

This paper proposes an impulse response shortening algorithm applicable to decision feedback equalization of single carrier wideband signal. When he impulse response shortening methods for narrowband signaling are applied to single carrier wideband signals, they result in noise enhancement problem, significantly deterioriting the receiver performance. This problem can be alleviated by educing the eigenvalue spread ratio of the impulse response, which can be achieved by adding additive white noise with small variance to the impulse response of the channel. The performance of the proposed scheme is verified by computer simulation.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2221-2229
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• 2022

In this research, for improving the measurement performance of Prompt Gamma-ray Neutron Activation Analysis (PGNAA) set-up, a new optimization method for set-up design was proposed and investigated. At first, the calculation method for Signal-to-Noise Ratio (SNR) was proposed. Since the SNR could be calculated and quantified accurately, the SNR was chosen as the evaluation parameter in the new optimization method. For discussing the feasibility of the SNR optimization method, two kinds of PGNAA set-ups were designed in the MCNP code, based on the SNR optimization method and the previous signal optimization method, respectively. Meanwhile, the single element spectra analysis method was proposed, and the analysis effect of single element spectra as well as element sensitivity were used for comparing the measurement performance. Since the simulation results showed the better measurement performance of set-up designed by SNR optimization method, the experimental set-ups were built for the further testing, finally demonstrating the feasibility of the SNR optimization method for PGNAA setup design.

• ETRI Journal
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• v.33 no.2
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• pp.176-183
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• 2011

This paper presents a new analytical approach and experimental verification for the improvement of noise performance in phased-array receivers. For analysis purposes, a multi-channel array system is converted into an equivalent single-channel system, such that the two presents the identical signal and noise powers at the output, respectively. We define an effective gain, noise figure, and signal-to-noise ratio in the equivalent system. Through the proposed approach, the noise performance of the array receiver is analyzed in a general and straightforward manner and then compared to that of each individual array channel. In addition, the phase noise of the array system is analyzed in a rigorous manner, showing its effective reduction by a factor of the array size. The predicted improvement of the noise performance is experimentally confirmed with a CMOS integrated phased-array receiver.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.