• Journal of Power Electronics
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• 제9권1호
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• pp.124-131
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• 2009

This paper presents a PWM dc-ac converter regulation using a Single Input Fuzzy PI Controller (SIFPIC). The SIFPIC is derived from the signed distanced method, which is a simplification of a conventional fuzzy controller. The simplification results in a one-dimensional rule table, that allows its control surface to be approximated by a piecewise linear relationship. The controller multi-loop structure is comprised of an outer voltage and an inner current feedback loop. To verify the performance of the SIFPIC, a low power PWM dc-ac converter prototype is constructed and the proposed control algorithm is implemented. The experimental results show that the SIFPIC performance is comparable to a conventional Fuzzy PI controller, but with a much reduced computation time.

• 대한전자공학회논문지TC
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• 제43권1호
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• pp.1-8
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• 2006

새로운 형태의 RER(Radio Frequency IDentification) 리더용 안테나 구조를 제안하였다. 기존의 RFB 리더용 안테나는 단일 루프 안테나를 사용한다. 리더용 단일 루프 안테나는 통상 트랜스폰더에 비하여 큰 사이즈를 가지며 이와 같은 경우 루프 안테나의 가운데 부분에는 자계 필드가 약하다. 본 논문에서는 병렬 루프 안테나를 제안하고, 단일 루프 안테나와 직렬 루프 안테나 그리고 병렬 루프 안테나를 전산모의실험 및 측정하였다. 전산모의실험 결과 안테나의 중앙부분에서 단일 루프 안테나의 경우 약 0.40A/m, 로 가장 낮은 수치를 보였고, 직렬 급전 다중 루프 안테나의 경우 약 0.68A/m 로 단일 루프 안테나에 비해 약간 높은 수치를 보였으며, 병렬 급전 다중 루프 안테나의 경우 약 1.98A/m 로 단일 루프 안테나와 직렬 급전 다중 루프 안테나에 비해 상당히 높은 자계 필드를 보였다. 구현한 각각의 안테나에 저항을 직렬로 연결하여 20Vp-p의 입력 전압을 인가하고, 무선인식 카드의 경우와 유사하게 비교하기 위해 넓이가 $79mm{\time}48mm$ 인 측정용 태고에 유도된 전압을 각 안테나의 중앙부분에서 거리를 증가시키면서 측정하였다. 본 논문에서 제안하는 병렬 급전 다중 루프 안테나는 안테나의 중앙부분에서 유도전압이 약 4.04V 로서 단일 루프 안테나의 약 0.76V, 직렬 급전 다중 루프 안테나의 약 1.45V 보다 높은 유도 전압을 보였다. 실험결과에서 볼 수 있듯이 제안된 병렬급전 다중 루프 안테나는 유도되는 전압이 상대적으로 높아 가독거리가 증가 될 수 있다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Journal of Power Electronics
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• 제15권6호
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• pp.1456-1467
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• 2015

This paper presents a novel close-loop control scheme based on small signal modeling and weighted composite voltage feedback for a three-phase input and single-phase output Matrix Converter (3-1MC). A small non-polar capacitor is employed as the decoupling unit. The composite voltage weighted by the load voltage and the decoupling unit voltage is used as the feedback value for the voltage controller. Together with the current loop, the dual-loop control is implemented in the 3-1MC. In this paper, the weighted composite voltage expression is derived based on the sinusoidal pulse-width modulation (SPWM) strategy. The switch functions of the 3-1MC are deduced, and the average signal model and small signal model are built. Furthermore, the stability and dynamic performance of the 3-1MC are studied, and simulation and experiment studies are executed. The results show that the control method is effective and feasible. They also show that the design is reasonable and that the operating performance of the 3-1MC is good.

• 한국태양에너지학회 논문집
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• 제32권spc3호
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• pp.245-254
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• 2012

In photovoltaic system, the characteristics of photovoltaic module such as open circuit voltage and short circuit current will be changed because of cell temperature and solar radiation. Therefore, the boost converter of a PV system connects between the output of photovoltaic system and DC link capacitor of grid connected inverter as controlling duty ratio for maximum power point tracking(MPPT). This paper shows the dynamic characteristics of the boost converter by comparing single-loop and two-loop control algorithm using both analog and digital control. Both proposed compensation methods have been verified with computer simulation to demonstrate the validity of the proposed control schemes.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2354-2363
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• 2018

This paper proposed a novel double closed control strategy for single-phase voltage source pulse width modulation (PWM) rectifier based on active disturbance rejection control (ADRC) and dq current decoupling control. First, the mathematical model of the single-phase PWM rectifier in the d-q axis synchronous rotating reference frame is established by constructing a virtual component using a second-order generalized integrator (SOGI). Then, the mathematical model is simplified according to the active power conservation, and the first-order equation of single-phase PWM rectifier voltage outer loop is acquired. A linear auto-disturbance rejection controller is used to design the voltage outer loop according to the first-order equation. Finally, the proposed control strategy and the traditional PI control are compared and verified by simulation and physical experiments. Both simulation and experimental results confirm that the proposed control strategy has excellent dynamic performance and strong rejection ability to disturbances.

• 전력전자학회논문지
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• 제23권4호
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• Journal of Power Electronics
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• 제13권5호
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• pp.829-840
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• 2013

The modified sinusoidal pulse-width modulation (SPWM) is one of the PWM techniques used in three-phase AC-DC buck converters. The modified SPWM works without the current sensor (the converter is current sensorless), improves production of sinusoidal AC current, enables obtainment of near-unity power factor, and controls output voltage through modulation gain (ranging from 0 to 1). The main problem of the modified SPWM is the huge starting current and voltage (during transient) that results from a large step change from the reference voltage. When the load changes, the output voltage significantly drops (through switching losses and non-ideal converter elements). The single-input single-output (SISO) approach with minor-loop voltage feedback controller presented here overcomes this problem. This approach is created on a theoretical linear model and verified by discrete-model simulation on MATLAB/Simulink. The capability and effectiveness of the SISO approach in compensating start-up current/voltage and in achieving zero steady-state error were tested for transient cases with step-changed load and step-changed reference voltage for linear and non-linear loads. Tests were done to analyze the transient performance against various controller gains. An experiment prototype was also developed for verification.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• ETRI Journal
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• 제38권2호
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• pp.217-226
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• 2016

We propose an architecture that reduces the power consumption and active area of such a modulator through a reduction in the number of active components and a simplification of the topology. The proposed architecture reduces the power consumption and active area by reducing the number of active components and simplifying the modulator topology. A novel second-order loop filter that uses a single operational amplifier resonator reduces the number of active elements and enhances the controllability of the transfer function. A trapezoidal-shape half-delayed return-to-zero feedback DAC eliminates the loop-delay compensation circuitry and improves pulse-delay sensitivity. These simple features of the modulator allow higher frequency operation and more design flexibility. Implemented in a 130 nm CMOS technology, the prototype modulator occupies an active area of $0.098mm^2$ and consumes 5.23 mW power from a 1.2 V supply. It achieves a dynamic range of 62 dB and a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz. The figure-of-merit of the modulator is 191 fJ/conversion-step.