• Journal of Power Electronics
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• v.14 no.3
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• pp.507-518
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• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.3
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• pp.423-431
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• 2002

An experimental study is conducted to investigate the effect of two-frequency forcing on turbulent flow behind a backward-facing step at the Reynolds number of 27000 based on the step height. The forcing is provided from a thin slit located at the edge of the backward-facing step to increase mixing behind the backward-facing step and consequently to reduce the reattachment length. With single frequency forcing, the minimum reattachment length is obtained at the non-dimensional forcing frequency (F) of St$\_$h/ = 0.29. With two-frequency forcing, a subharmonic frequency (F/2) or biharmonic frequency (2F) is combined with the fundamental frequency (F), i.e. (F, F/2) or (F, 2F) forcing is applied. In the case of (F, F/2) forcing, the reattachment length is not much sensitive to the phase difference between F and F/2. However, the reattachment length significantly depends on the phase difference between F and 2F in the case of (F, 2F) forcing. At a certain range of the phase difference, the reattachment length becomes smaller than that of the single frequency forcing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.641-648
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• 2011

Frequency domain equalization is the most promising technology that has relatively low complexity in multipath channel. A frame of single carrier system with frequency domain equalization (SC-FDE) has cyclic prefix to mitigate effect of delay spread. After synchronization and equalization procedure on the SC-FDE system, common phase offset (CPO) that can introduce performance degradation caused by phase mismatch between transmitter and receiver oscillators is remained. In this paper, common phase offset tracking in frequency domain is proposed. To track CPO, constant amplitude zero autocorrelation code sequence as training sequence is adopted. By using numerical results, performance of mean square error is evaluated. The results show that MSE of CPO has similar performance compare to the time-domain estimation and there is no need of domain conversion.

• Journal of the Korean Solar Energy Society
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• v.32 no.6
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• pp.106-112
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• 2012

As a fuel cell converts the chemical energy of the fuel cell into electrical energy by electrochemical reaction, the fuel cell system is uniquely integrated technique including fuel processor, fuel cell stack, power conditioning system. The residential fuel cell-PCS(Power Conditioning System) needs to convert efficiently the DC current produced by the fuel cell into AC current using single-phase DC-AC inverter. A single-phase DC-AC inverter has naturally low frequency ripple which is twice frequency of the output current. This low frequency(120Hz) ripple reduces the efficiency of the fuel cell. This paper presents notch filter with IP voltage controller to reject specific 120Hz current ripple in single-phase inverter. The notch filter is designed that suppress just only specific frequency component and no phase delay. Finally, the proposed notch filter design method has been verified with computer simulation and experimentation.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1037-1044
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• 2019

This study describes injection locking phenomena for multi-frequency generator design. For the design of the multi-frequency generator, we describe the basic theory of injection locking phenomenon and conduct a single injection locking experiment based on it. The experiments was conducted by applying injection signals that vibrates consistently to oscillators which vibrates unstablely compared to injection signals. Injection signal was applied using a Howland current source and circuit was designed using a Colpitts oscillator. The results of the experiment showed that each oscillator oscillates reliable when injection signals(840kHz, 500kHz) are injected. Through the results of a single injection locking experiment, it is confirmed that injection locking phenomena can be applied in the design of the multi-frequency generator.

• Journal of Broadcast Engineering
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• v.17 no.5
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• pp.864-875
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• 2012

In this paper, we propose a carrier frequency offset estimation method for single-carrier MIMO systems. In the proposed method, phase rotated PN (Pseudo-Noise) sequences are transmitted to prevent a cancelling out of partial PN sequences. After removing a modulation of received PN sequences by multiplying of complex conjugated PN Sequences which are locally generated in receiver, a CFO (Carrier Frequency Offset) is accurately estimated by employing L&R method which is a kind of ML (Maximum Likelihood) estimation algorithm and uses multiple auto-correlatos. In addition, the frequency offset estimation scheme by using channel state information is proposed for accurate CFO estimation in time-varying Rayleigh channel. By performing computer simulations, MSE (Mean Square Error) performance of proposed method is almost same as MSE performance of SISO systems in AWGN channel. Moreover, MSE Performance of proposed method with using channel information is higher than MSE performances of SISO system and conventional method in time-varying Rayleigh channel.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.

• Korean Journal of Optics and Photonics
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• v.22 no.5
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• pp.223-229
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• 2011

We present a low jitter frequency up-conversion detector based on quasi-phase matched sum frequency generation in a periodically poled $LiNbO_3$ waveguide for efficient single-photon detection at 1.5 ${\mu}m$ telecommunication wavelengths. The maximum detection efficiency and the noise count rate using the pump power of 300 mW and the pump wavelength of 974 nm are about 7% and 480 kHz, respectively. We also characterize the timing jitter of the frequency up-conversion detector by analyzing the time distribution of the detection outputs for photons generated through a picosecond pump pulsed spontaneous parametric downconversion. The minimum timing jitter was measured to be about 39.1 ps. Coincidence measurement with a narrow time window for pulsed up-conversion photons can eliminate the unwanted noise counts and maximize signal to noise ratio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5C
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• pp.295-301
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• 2011

In [1], it has been shown that the energy spreading transform (EST) based iterative equalizer (IE) could enhance its performance by improving the reliability of the decision feedback symbols without the help of the complicated channel decoder. In the matched filter (MF) based IE proposed in [1], however, its feedforward filter (FFF) has been designed in the frequency domain while its feedback filter (FBF) in the time domain. So its complexity increases proportional to the channel memory length. To solve this problem, in this paper, both FFF and FBF are designed in the frequency domain. This enables the proposed frequency domain IE (FD-IE) to achieve the lower complexity over the conventional method in the highly dispersive channel. In addition, simulation results demonstrate that the BER performance of the proposed method is the same as the conventional.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.5
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• pp.25-32
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• 2007

This paper proposes a distributed space-frequency block code (SFBC) for relay-assisted single carrier frequency-domain equalization (SC-FDE). The proposed technique achieves spatial diversity gain over fast fading channels without the complexity of multiple antennas. The mobile equipment of the proposed system has a very simple transmitter structure with constant amplitude transmit sequences, which is desirable especially for uplink communications. In order to obtain spatial diversity, the transmit sequence of relay is efficiently generated in the time domain, which is equivalent to the SFBC. Further, efficient implementation of relay and destination structures is also presented. Extensive simulation results show that the proposed system significantly outperforms the distributed space-time block code (D-STBC) SC-FDE over fast fading channels.