• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.16 no.12 s.117
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• pp.1272-1278
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• 2006

This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin(Au/Sn) eutectic solder bonding. The membrane chip has $2.5mm{\times}2.5mm$, 0.5${\mu}m$ thick low stress silicon nitride membrane, $2mm{\times}2mm$ Au/Ni/Cr membrane electrode, and 3${\mu}m$ thick Au/Sn layer. The backplate chip has $2mm{\times}2mm$, 150${\mu}m$ thick single crystal silicon rigid backplate, $1.8mm{\times}1.8mm$ backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50{\sim}60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is 39.8 ${\mu}V/Pa$(-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.305-310
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• 2013

In this paper, the pressure sensor usable in a high temperature, using a SDB(silicon-direct-bonding) wafer of Si/$SiO_2$/Si-sub structure was provided and studied the characteristic thereof. The pressure sensor produces a piezoresistor by using a single crystal silicon as a first layer of SDB wafer, to thus provide a prominent sensitivity, and dielectrically isolates the piezoresistor from a silicon substrate by using a silicon dioxide layer as a second layer thereof, to be thus usable even under the high temperature over $120^{\circ}C$ as a limited temperature of a general silicon sensor. The measured result for a pressure sensitivity of the pressure sensor has a characteristic of high sensitivity, and its tested result for an output of the sensor further has a very prominent linearity and hysteresis characteristic.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.156-161
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• 2011

The present study introduces a novel wet etching technique for nanostructure fabrications which usually requires low surface roughness. Using the current method, acquired profiles were smooth even in the nanoscale, which cannot be easily achieved with conventional wet or dry etching methods. As one of the most popular single crystal silicon etchant, potassium hydroxide (KOH) solution was used as a base solvent and two additives, antimony trioxide (Sb2O3) and ethyl alcohol were employed in. Four experimental parameters, concentrations of KOH, Sb2O3, and ethyl alcohol and temperature were optimized at 60 wt.%, 0.003 wt.%, 10 v/v%, and $23^{\circ}C$, respectively. Effects of additives in KOH solution were investigated on the profiles in both (110) and (111) planes of single crystal silicon wafer. The preliminary results show that additives play a critical role to decrease etch rate significantly down to ~2 nm/min resulting in smooth side wall profiles on (111) plane and enhanced surface roughness.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.5
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• pp.831-836
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• 2013

This study demonstrates the process of fabricating patterns using tribonanolithography (TNL),with laboratory-made micro polycrystalline diamond (PCD) tools that are attached to an atomic force microscope (AFM). The various patterns are easily fabricated using mechanical scratching, under various normal loads, using the PCD tool on single crystal silicon, which is the master mold for replication in this study. Then, polydimethylsiloxane (PDMS) replica molds are fabricated using precise pattern transfer processes. The transferred patterns show high dimensional accuracy as compared with those of TNL-processed silicon micro molds. TNL can reduce the need for high cost and complicated apparatuses required for conventional lithography methods. TNL shows great potential in that it allows for the rapid fabrication of duplicated patterns through simple mechanical micromachining on brittle sample surfaces.

• Journal of Electrical Engineering and Technology
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• v.6 no.1
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• pp.119-122
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• 2011

A new high speed AFM probe has been proposed and fabricated. The probe is integrated with PZT actuated cantilever realized in bulk silicon wafer using heavily boron doped silicon as an etch stop layer. The cantilever thickness can be accurately controlled by the boron diffusion process. Thick SCS cantilever and integrated PZT actuator make it possible to be operated at high speed for fast imaging. The resonant frequency of the fabricated probe is 92.9 kHz and the maximum deflection is 5.3 ${\mu}m$ at 3 V. The fabricated probe successfully measured the surface of standard sample in an AFM system at the scan speed of 600${\mu}m$/sec.

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.452-455
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• 2002

Single crystal 3C-SiC(cubic silicon carbide) thin-films were deposited on Si(100) substrate up to a thickness of $4.3{\mu}m$ by APCVD method using HMDS(hexamethyildisilane) at $1350^{\circ}C$. The HMDS flow rate was 0.5 sccm and the carrier gas flow rate was 2.5 slm. The HMDS flow rate was important to get a mirror-like crystal surface. The growth rate of the 3C-SiC films was $4.3{\mu}m/hr$. The 3C-SiC epitaxical films grown on Si(100) were characterized by XRD, AFM, RHEED, XPS and raman scattering, respectively. The 3C-SiC distinct phonons of TO(transverse optical) near $796cm^{-1}$ and LO(longitudinal optical) near $974{\pm}1cm^{-1}$ were recorded by raman scattering measurement. The heteroepitaxially grown films were identified as the single crystal 3C-SiC phase by XRD spectra$(2{\theta}=41.5^{\circ})$.

• Journal of Magnetics
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• v.9 no.4
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• pp.116-120
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• 2004

Hexagonal barium-ferrite ($BaFe_{12}O_{19}$, magnetoplumbite structure; BaM) film with perpendicularly c-axis orientation was successfully deposited on (100) silicon substrates with an MgO (111) underlayer by rf diode sputtering and in-situ heating at $920^{\circ}C$. The magnetic and structural properties of 0.27 ${\mu}m$ thick BaM films on MgO (111) underlayers were compared to films of the same thickness deposited onto single-crystal MgO (111) and c-plane ($000{\ell}$) sapphire ($Al_2O_3$) substrates by vibrating sample magnetometry (VSM), x-ray diffractometer (XRD), and atomic force microscopy (AFM). The thickness dependence of MgO (111) underlayers on silicon wafer was found to have a large effect on both magnetic and structural properties of the BaM film. The thickness of 15 nm MgO (111) underlayers produced BaM films with almost identical magnetic and structural properties as the single-crystal substrates; this can be explained by the lower surface roughness for thinner underlayer thicknesses. The magnetization saturation ($M_s$) and the ratio $H_{cII}/H_{c{\bot}}$ for the BaM film with a 15 nm MgO (111) underlayer is 217 emu/cc and 0.24, respectively. This is similar to the results for the BaM films deposited on the single-crystal MgO (111) and sapphire substrates of 197 emu/cc and 0.10, 200 emu/cc and 0.12, respectively. Therefore, the proposed MgO (111) underlayer can be used in many applications to promote c-axis orientation without the cost of expensive substrates.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.12
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.395-400
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• 2005

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin damaged layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The damaged layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.