• Journal of Institute of Control, Robotics and Systems
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• v.6 no.2
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• Journal of Korea Multimedia Society
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• v.14 no.12
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• pp.1517-1527
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• 2011

This paper presents a motion capture based rehabilitation training system for a lower-limb paretic patient. The system evaluates the rehabilitation status of the patient by using the bend posture of the knees and the weight balance of the body. The posture of both legs is captured with a single camera using the planar mirror. The weight distribution is obtained by the Wii Balance Board. Self-occlusion problem in the tracking of the legs is resolved by using k-nearest neighbor based clustering with body symmetry and local-linearity of the posture data. To do this, we present data normalization and its symmetric property in the normalized vector space.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.688-691
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• 2009

항공기에는 각각의 임무에 맞게 설계된 많은 종류의 임무컴퓨터(Mission Computer)가 존재한다. 여러 센서(Sensor)에서 전송되는 신호를 처리하는 기존의 단일코어 기반 임무컴퓨터는 항공기의 성능 향상에 따른 임무 요구도의 증대와 전장 환경의 변화에 따라 기내 데이터의 양이 급격히 증가하여 정보통신의 실시간성에 한계를 보인다. 본 논문에서는 실시간 운영체제인 VxWorks를 통해서 다중채널 ARINC-429 통신모듈을 실시간으로 제어하는 멀티코어 SBC(Single Board Computer) 테스트베드(Test-Bed)를 제시한다.

• Journal of IKEEE
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• v.20 no.1
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• pp.89-93
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• 2016

In this paper, we proposed SIMT based Image Signal Processor which can apply various image preprocessing algorithms and allow parallel processing of application programs such as image recognition. Conventional ISP has the hard-wired image enhancement algorithm of which the processing speed is fast, but there was difficult to optimize performance depending on various image processing algorithms. The proposed ISP improved the processing time applying SIMT architecture and processed a variety of image processing algorithms as an instruction based processor. We used Xilinx Virtex-7 board and the processing time compared to cell multicore processor, ARM Cortex-A9, ARM Cortex-A15 was reduced by about 71 percent, 63 percent and 33 percent, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2519-2523
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• 2003

Ultrasonic sensors are widely used in mobile robot applications to recognize external environments, because they are cheap, easy to use, and robust under varying lighting conditions. In most cases, a single ultrasonic sensor is used to measure the distance to an object based on time-of-flight (TOF) information, whereas multiple sensors are used to recognize the shape of an object, such as a corner, plane, or edge. However, the conventional sequential driving technique involves a long measurement time. This problem can be resolved by pulse coding ultrasonic signals, which allows multi-sensors to be fired simultaneously and adjacent objects to be distinguished. Accordingly, the current presents a new simultaneous coded driving system for an ultrasonic sensor array for object recognition in autonomous mobile robots. The proposed system is designed and implemented using a DSP and FPGA. A micro-controller board is made using a DSP, Polaroid 6500 ranging modules are modified for firing the coded signals, and a 5-channel coded signal generating board is made using a FPGA. To verify the proposed method, experiments were conducted in an environment with overlapping signals, and the flight distances for each sensor were obtained from the received overlapping signals using correlations and conversion to a bipolar PCM-NRZ signal.

• Journal of Korea Game Society
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• v.10 no.1
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• pp.105-113
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• 2010

It takes quite amount of time to study a board game because there are many game characters and different stages are exist for board games. Also, the opponent is not just a single character that means it is not one on one game, but group vs. group. That is why strategy is needed, and therefore applying optimum learning is a must. If there were equal result that both are considered to be best ones during the course of learning stage, Heuristic which utilizes learning of problem area of Jul-Gonu was used to improve the speed of learning. To compare a normal character to an improved one, a jul-gonu game was created, and then they fought against each other. Improved character considered distance and attacked other one. As a result, improved character's ability was improved on learning speed.

• Journal of Korea Game Society
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• v.15 no.2
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• pp.95-104
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• 2015

Many games for English vocabulary learning, such as hangman, cross puzzle, matching, etc, have been developed which are of board-type or computer game-type. Most of these computer games are adapting strategy-style game plays so that there is a limit on giving the fun, a nature of games, to learners who do not like games of this style. In this paper, a system for memorizing new English words is proposed which is based on a single-player car racing game targeting youths and adults. In the game, the core of our system, a learner drives a car and obtains game points by colliding with English word texts like game items appearing on the track. The learner keeps on viewing English words being exposed on the track while driving, resulting in memorizing those words according to a learning principle stating viewing is memorization. To our experiment, the effect of memorizing English words by our car racing game is good, and the degree of satisfaction with our system as a English vocabulary learning tool is reasonably high. Also, previous word games are suitable for the memory enforcement of English words but our game can be used for the memorization of new words.

• The Journal of Engineering Research
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• v.2 no.1
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• pp.39-47
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• 1997

This paper presents a single board digital signal processing system which can perform two-dimensional (2-D) digital infinite impulse response (IIR) filtering in realtime. We have developed an architecture to provide not only the necessary computational power but also a balance of the system input/output and computational requirements. The architecture achieves large system throughput by using highly parallel processing at both the system and processor levels. It reduces system data communication requirements significantly by taking advantage of a custom-designed processor and by providing each processor with its own input and ouput channel. After system initialization, almost 100 percent of the time is used for data processing. Data transfers occur concurrently with data processing. The functional level simulation reveals that the system throughput can reach as high as one pixel per system cycle. With only 10MHz clock frequency system, it can implement up to fourth order 2-D IIR filters for video-rate data ($512\times512$ pixels per frame at 30 frames per second). If we increase the system frequency, the system can be used for the preprocessing and postprocessing of video signal of HDTV.

• Proceedings of the KSRS Conference
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• 2005.10a
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• pp.593-596
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• 2005

The MSC is a remote sensing instrument with very high performance that is to be installed on KOMPSAT2 satellite. The MSC consists of EOS (Electro-Optic Subsystem), PMU (Payload Management Unit) and PDTS (Payload Data Transmission Subsystem). PMU controls and monitors all the other payload units by sending commands and collecting telemetry. PMU is in charge of interfacing between payload system and satellite bus system. PMU gets commands from ground-station via OBC (On-Board Computer) that is a main controller of the satellite bus system and sends telemetry to the ground-station via OBC. There is a processor module, called SBC (Single Board Computer) in the PMU. The SBC is a main controller of the MSC system. The main roles of the SBC are payload mission management, command validation and execution, telemetry collection and monitoring, ancillary data handling, event reporting, power control of payload sub-units and communication with these units. Intel's 80486DX2 processor has been used for the SBC. Due to the fact that the SBC plays important roles for imaging mission execution and handles a lot of control data that is required for payload operation, it is required to make analysis of the CPU load when it is in maximum operation mode. In this paper, the analysis and measurement results of the SBC throughput in the maximum operation mode.

• Journal of Astronomy and Space Sciences
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• v.13 no.2
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• pp.149-162
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• 1996

The results of space radiation experiments carried out on board the first two Korean technology demonstration microsatellites are presented in this paper. The first satellite, KITSAT-1, launched in August 1992, carries a radiation monitoring payload called cosmic ray experiment(CRE) for characterizing the low-earth orbit(LEO) radiation environment. The CRE consists of two sub-systems: the cosmic particle experiment (CPE) and the total dose experiment(TDE). In addition, single event upset(SEU)rates of the program memory and the RAM disk are also monitored. The second satellite, KITSAT-2, launched in September 1993, carries a newly developed 32-bit on-board computer(OBC), KASCOM(KAIST satellite computer in addition to OBC186. SEUs ocurred in the KASCOM, as well as in the program memory and RAM disk memory, have been monitored since the beginning of the satellite operation. These two satellites, which are very similar in structures but different in orbits, provide a unique opportunity to study the effects of the radiation environment characterized by the orbit.