• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.2
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• pp.101-105
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• 2006

The Engineering Model of STSAT-2 on-board computer(OBC) was developed and tested completely with other sub-systems. The on-board computer of STSAT-2 has a high- performance PowerPC processors and a structure of centralized network communication. In addition, a lot of logics are implemented by Field Programmable Gate Array, such as interrupt controller, watchdog timer and UART. It could make the weight and size of OBC lighter and smaller. Also, the STSAT-2 on-board computer has more improved tolerance against Single Event Upsets and faults than that of the STSAT-1.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.4
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• pp.389-394
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• 2010

This paper describes the conceptual design of mass memory unit for high speed data processing and mass memory management in the STSAT-3 compared to that of STSAT-2. The FPGA directly controls the data receiving from two payloads with the maximum 100Mbps speed and 32Gb mass memory management to satisfy these requirements. We used SRAM-based FPGA from XILINX having fast operating speed and large logic cells. Therefore, the Triple Modular Redundancy(TMR) and configuration memory scrubbing techniques will also be used to protect FPGA from Single Event Upset(SEU) in space.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.4
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• pp.105-111
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• 2003

Qualification Model of On-board Computer (OBC) for KAISTSAT-4 was developed. The OBC of KAISTASAT-4 has some improved features compared with that of KAISTSAT-3: To reduce weight and size of OBC many logics are implemented by FPGAs, and a network controller is included in OBC to access the satellite network with high speed. Also, the developed OBC has an improved tolerance against SEUs and faults. The OBC was fully tested under simulated space environment with no errors.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.2
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• pp.56-67
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• 2006

The reliability and failure mode effect analysis are effective means to achieve efficient and cost-reduction design for satellite development. The failure rate of COTS (Commercial-Off-The-Shelf) parts required for reliability analysis is not usually provided from the manufacturer. Space environment factors based on empirical data obtained from MIL-HDBK-217F can be applicable to the reliability calculation. As a radiation environment factor, the occurrence rate of SEL (Single Event Latch-up) is additionally incorporated for the failure rate prediction. In this paper, the statistical reliability analysis method for low-cost small satellite using COTS parts is suggested. This statistical reliability analysis was applied to HAUSAT-2 small satellite whose electronic boxes are consisted of many COTS parts to calculate the system reliability at the end of design mission life.

• Proceedings of the KSRS Conference
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• 2004.10a
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• pp.452-455
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• 2004

MSC (Multi-Spectral Camera) system is a remote sensing instrument to obtain high resolution ground image. EOS (Electro-Optic System) for MSC mainly consists of PMA (Primary Mirror Assembly), SMA (Secondary Mirror Assembly), HSTS (High Stability Telescope Structure) and DFPA (Detector Focal Plane Assembly). High performance of EOS makes it possible for MSC system to provide high resolution and high quality ground images. Temperature of the EOS needs to be controlled to be in a specific range in order not to have any thermal distortion which can cause performance degradation. It is controlled by full redundant CPU based electronics. The validity of thermistor readings can be checked because a few thermistors are installed on each control point on EOS. Various kinds of thermal control logics are used to prevent 'Single Point Failure'. Control logic has a few set of database in order not to be corrupted by SEU (Single Event Upset). Even though the thermal control logic is working automatically, it can also be monitored and controlled by ground-station operator. In this paper, various ways of thermal control logic for EOS in MSC will be presented, which include thermal control mode and logic, redundancy design and status monitoring and reporting scheme.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.437-442
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• 2021

This study describes the design and implementation of power supply of dehop/rehop transponder of EQM(Engineering Qualification Model). We materialized the interface of the PLDIU and power supply of a satellite bus, and minimized the potential for the occurrence of such erroneous operation circuit ESD through the WCA of the space environment. We designed a reliable power supply through simulation for TID about space radiation and simulation of the vibration generated during it launched, and we confirmed that it satisfies the environmental test specification through the test space environment after production.

• Journal of Astronomy and Space Sciences
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• v.13 no.2
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• pp.149-162
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• 1996

The results of space radiation experiments carried out on board the first two Korean technology demonstration microsatellites are presented in this paper. The first satellite, KITSAT-1, launched in August 1992, carries a radiation monitoring payload called cosmic ray experiment(CRE) for characterizing the low-earth orbit(LEO) radiation environment. The CRE consists of two sub-systems: the cosmic particle experiment (CPE) and the total dose experiment(TDE). In addition, single event upset(SEU)rates of the program memory and the RAM disk are also monitored. The second satellite, KITSAT-2, launched in September 1993, carries a newly developed 32-bit on-board computer(OBC), KASCOM(KAIST satellite computer in addition to OBC186. SEUs ocurred in the KASCOM, as well as in the program memory and RAM disk memory, have been monitored since the beginning of the satellite operation. These two satellites, which are very similar in structures but different in orbits, provide a unique opportunity to study the effects of the radiation environment characterized by the orbit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.91-102
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• 2005

Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.