• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.235-238
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• 2001

Deformation phase can be obtained by using Least-Square Fitting. In extraction of phase values, Least-Square Fitting is superior to usual method like as 2, 3, 4-Bucket Algorithm. That can extract almost noise-free phase and retain 2$\pi$discontinuities. But more fringe in phase map, 2$\pi$ discontinuities is destroyed when that is filtered and reconstruction of deformation is not reliable. So, we adapted Least-Square Fitting using an isotropic window in dense fringe. using Sine-Cosine filter give us perfect 2$\pi$discontinuities information. We showed the process and result of extraction of phase map and filtering in this paper.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.12
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• pp.20-26
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• 2002

Deformation phase can be obtained by using Least-Square fitting. In extraction of phase values, Least-Square Fitting is superior to usual method such as 2, 3, 4-Bucket Algorithm. That can extract almost noise-free phase and retain 2 $\pi$ discontinuities. But more fringes in phase map, 2 $\pi$ discontinuities are destroyed when that are filtered and reconstruction of deformation is not reliable. So, we adapted Least-Square fitting using an isotropic window in dense fringe. Using Sine/cosine filter give us perfect 2 $\pi$ discontinuities information. We showed the process and result of extraction of phase map and filtering in this paper.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.9
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• pp.4467-4486
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• 2016

Discrete cosine transform (DCT) based JPEG standard significantly improves the coding efficiency of image compression, but it is unacceptable event in serious blocking artifacts at low bit rate and low efficiency of high-definition image. In the light of all phase digital filtering theory, this paper proposes a novel transform based on discrete sine transform (DST), which is called all phase discrete sine biorthogonal transform (APDSBT). Applying APDSBT to JPEG scheme, the blocking artifacts are reduced significantly. The reconstructed image of APDSBT-JPEG is better than that of DCT-JPEG in terms of objective quality and subjective effect. For improving the efficiency of JPEG coding, the structure of JPEG is analyzed. We analyze key factors in design and evaluation of JPEG compression on the massive parallel graphics processing units (GPUs) using the compute unified device architecture (CUDA) programming model. Experimental results show that the maximum speedup ratio of parallel algorithm of APDSBT-JPEG can reach more than 100 times with a very low version GPU. Some new parallel strategies are illustrated in this paper for improving the performance of parallel algorithm. With the optimal strategy, the efficiency can be improved over 10%.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.473-478
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• 2003

To detect motions of bodies, we have discussed them with two viewpoints; one is a detection algorithm, and another is the hardware implementation. The former is to find small terms expansions for sine/cosine functions. We researched Maclaurin and optimum expansions, and moreover to reduce hardware amounts, revised the expansions. The expansions don't include divide calculations, and the error is within 0.01%. As for the former problem, there is another approach also; that is the cordic method. The method is based on the rotation of a vector on the complex plain. It is simple iterations and don't require large logic. We examined the precision and convergence of the method on C-simulations, and implemented on HDL. The later problem is to make FPGA within small gates. We considered approaches to eliminate a divider and to reduce the bit number of arithmetic. We researched Newton-Raphson's method to get reciprocal numbers. The higher-order expression shows rapid convergence and doesn't be affected by the initial guess. It is an excellent algorithm. Using them, we wish to design a detector, and are developing it on a FPGA.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.345-350
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• 1986

This paper deseribes the design of a vector-coordinate rotation processor and the apporoximate evaluations of sine and consine based upon the use of residue number systems. The proposed algorithm results in a considerable improvement of computational speed as compared to the CORDIC algorithm. According to the results of computer simulation, the mean error of sine and cosine is 0.0025, and the mean error of coorcinate rotation arithmatic is 0.65. The proposed processor has the efficiency for the design and fabrication of integrated circuits, because it consists of an array of identical lookup tables.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.48-53
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• 2007

Some digital signal processing applications, such as FFT, request multiplications with a group(or, groups) of a few predetermined coefficients. In this paper, based on the modified CSD algorithm, an efficient multiplier design method for predetermined coefficient groups is proposed. In the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), and in the multiplier design used in 128 point $radix-2^4$ FFT, it is shown that the area, power and delay time can be reduced up to 34%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1891-1898
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• 2013

To efficiently execute 3D graphic APIs, such as OpenGL and Direct3D, special purpose arithmetic unit(SFU) which supports floating-point sine, cosine, reciprocal, inverse square root, base-two exponential, and logarithmic operations is designed. The SFU uses second order minimax approximation method and lookup table method to satisfy both error less than 2 ulp(unit in the last place) and high speed operation. The designed circuit has about 2.3-ns delay time under 65nm CMOS standard cell library and consists of about 23,300 gates. Due to its maximum performance of 400 MFLOPS and high accuracy, it can be efficiently applicable to mobile 3D graphics application.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1645-1650
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• 2015

This paper presents the 3-dimensional electromagnetic field analysis method and correction of sensor distortion that is used by a motor speed sensor. The magnetic sensors are being expanded due to lower price than the other speed sensors such as resolver and encoder. Magnetic sensor generates sine and cosine waves when the motor rotates. However, the sine and cosine signals are distorted due to magnetic noise, which makes the angle error of the sensor, generated near by the Hall element. This paper defines an optimal design variables by using the Taguchi method to minimize output distortion of the magnetic sensor and permanent magnet. To enhance reliability of the magnetic position sensor from sensitivity error, assembly amplitude mismatch and the electrical angle, 3-Dimensional electromagnetic finite element method and correction algorithm errors were performed in due of the magnetic sensor in order to improve the quality of the initial production model.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.106-114
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• 2016

In this paper, we propose an efficient integer inverse transform structure for vp9 decoder. The proposed structure is a hardware structure which is easy to control and requires less hardware resources, and shares algorithms for realizing entire DCT(Discrete Cosine Transform), ADST(Asymmetric Discrete Sine Transform) and WHT(Walsh-Hadamard Transform) in vp9. The integer inverse transform for vp9 google model has a fast structure, named butterfly structure. The integer inverse transform for google C model, unlike universal fast structure, takes a constant rounding shift operator on each stage and includes an asymmetrical sine transform structure. Thus, the proposed structure approximates matrix coefficient values for all transform mode and is used to matrix operation method. With the proposed structure, shared operations for all inverse transform algorithm modes can be possible with reduced number of multipliers compared to the butterfly structure, which in turn manages the hardware resources more efficiently.

• ETRI Journal
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• v.44 no.5
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• pp.837-848
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• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.