• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.51-54
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• 2000

This paper presents an efficient method for estimating maximum simultaneous switching noise(SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use ａ-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions. Our method predicts the maximum SSN values more accurately as compared to existing approaches even in more practical cases such that there exist some of output drivers not in transition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.235-240
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• 2007

A current-balancing segmented group-inverting transmitter is presented for multi-Gb/s single-ended parallel links. With an additional increase of 4 pins, 16-bit data is efficiently encoded to 20 pins to achieve the current balancing and eliminate the simultaneous switching noise. Since the proposed coding is a simple inversion-or-not transformation of pre-defined groups of binary data, it can be implemented with simplified logic circuits. The transmitter is designed with a $0.18{\mu}m$ CMOS technology, and simulated eye diagrams at 5Gb/s show dramatic improvements in signal integrity.

• ETRI Journal
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• v.31 no.2
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• pp.201-208
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• 2009

This paper proposes a spiral-shaped power island structure that can effectively suppress simultaneous switching noise (SSN) when the power plane drives high-speed integrated circuits in a small area. In addition, a new technique is presented which greatly improves the resonance peaks in a stopband by utilizing ${\lambda}$/4 open stubs on a conventional periodic electromagnetic bandgap (EBG) power plane. Both proposed structures are simulated numerically and experimentally verified using commercially available 3D electromagnetic field simulation software. The results demonstrate that they achieve better SSN suppression performance than conventional periodic EBG structures.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.10a
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• pp.131-175
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• 2000

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.933-939
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• 2008

In this paper, a new composite electromagnetic bandgap(EBG) structure using magnetic materials is proposed for simultaneous switching noise(SSN) suppression in the high-speed digital circuits. The proposed EBG structure has periodic unit cells of square-patches connected by spiral-shaped bridges. The magnetic materials are located on the unit cells of spiral-shaped EBG. The real part of the permeability shifts bandgap to the lower frequency region due to the increased effective inductance. The imaginary part of the permeability has magnetic loss that decreases parasitic LC resonance peaks from between the unit cells. As a result, the proposed structure has the lower cut-off frequency compared with conventional EBG structure and -30 dB SSN suppression bandwidth from 175 MHz to 7.7 GHz. The proposed structure is expected to improve the power integrity and reduce the size of the EBG power plane.

• 한국ITS학회:학술대회논문집
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• v.2007 no.10
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• pp.334-337
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• 2007

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.71-80
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• 2004

A new SSN(Simultaneous Switching Noise) model is presented, which can afford to investigate SSN due to integrated circuit package. It is shown that previous SSN models are not accurate enough to be practical since they do not take decoupling capacitor into account. In this paper, a new SSN model including the decoupling capacitor is developed. It is verified that the model has excellent agreement(within $5\%$ error) with HSPICE simulation which employs TSMC 0.18um CMOS process technology.

• Journal of electromagnetic engineering and science
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• v.6 no.1
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• pp.62-70
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• 2006

This paper presents a new power plane design method incorporating a single geometry derived from a unit cell of photonic bandgap(PBG) structure. This method yields constantly wide suppression of parallel plate resonances from 0.9 GHz to 4.2 GHz and is very efficient to eliminate PCB resonances in a specified frequency region to provide effective suppression of simultaneous switching noise(SSN). It is shown that with only two cells the propagation of unwanted high frequency signals is effectively suppressed, while it could provide continuous return signal path. The measured results agree very well with theoretically predicted ones, and confirm that proposed method is effective for reducing EMI, with measured near-field distribution. The proposed topology is suitable for design of high speed digital system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.206-212
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• 2007

In this paper, a novel power/ground plane using the hybrid-cell electromagnetic band-gap(EBG) structure is proposed for the wide-band suppression of the ground bound noise(GBN) or simultaneous switching noise(SSN). The -30 dB stopband of the proposed structure starts from a few hundred MHz where the GBN/SSN energy is dominant. The distinctive features of this new structure are the thin spiral strip line and hybrid-cells. They realize the enhanced inductance and the shorter period of the EBG lattice. As a result, the lower cut-off frequency and bandwidth of the -30 dB stopband becomes lower and wider, respectively. In addition, the proposed structure has smaller number of resonance modes between power/ground planes and performs a low EMI behavior compared with the reference board.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.29-36
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• 2009

Power supply noise is fundamentally caused by large current peaks. Since large current peaks are induced by simultaneous switching of many circuit elements, power supply noise can be minimized by deliberate clock scheduling which utilizes nonzero clock skew. In this paper, nonzero skew clock scheduling is used to avoid the large peak current and consequently reduce power supply noise. While previous approaches require extra characterization efforts to acquire current waveform of a circuit, we approximate it only with existing cell library information to be easily adapted to conventional design flow. A simulated annealing based algorithm is performed, and the peak current values are estimated for feasible clock schedules found by the algorithm. The clock schedule with the minimum peak current is selected for a solution. Experimental results on ISCAS89 benchmark circuits show that the proposed method can effectively reduce the peak current.