• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.777-779
• /
• 1999

A new distributed/parallel algorithm simulator, DASim(Distributed Algorithm Simulator), is proposed in this paper. The idea is to ease the task of design, analysis and implementation of distributed algorithms. A small high level language has been proposed for the purpose. Through this non-language specific high level language, the users are spared from the tedious details about how to program distributed or parallel algorithms. Further, visualization of these algorithms are pretty helpful to understand behaviors of these algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.1B
• /
• pp.71-79
• /
• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.4
• /
• pp.1425-1437
• /
• 2018

In this paper, a methodology was proposed to reduce the electrical level and spatial size of the smart grid with distributed generations (DGs) to a scale in which the electrical phenomena and control strategies for disturbances on the smart grid could be safely and freely experimented and observed. Based on the design methodology, a micro smart grid simulator with a substation transformer capacity of 190VA, voltage level of 19V, maximum breaking current of 20A and size of $2{\times}2m^2$ was designed by reducing the substation transformer capacity of 45MVA, voltage level of 23kV and area of $2{\times}2km^2$ of the smart grid to over one thousandth, and also reducing the maximum breaking current of 12kA of the smart grid to 1/600. It was verified that the proposed design methodology and designed micro smart grid simulator were very effective by identifying how all of the fault currents are limited to within the maximum breaking current of 20A, and by confirming that the maximum error between the fault currents obtained from the fault analysis method and the simulation method is within 1.8% through the EMTP-RV simulation results to the micro smart grid simulator model.

• Journal of KIISE:Computing Practices and Letters
• /
• v.11 no.3
• /
• pp.257-267
• /
• 2005

The real-time operating system(RTOS) simulator, one of the tools provided by RTOS development environment, allows users to develop and debug application programs even before the target hardware is ready. Thus, most of commercial RTOS development environments provide with RTOS simulator for the purpose. But they are implemented to simulate only functional aspects on a host system, so that it is not possible to estimate execution time of application programs on the target hardware. Since the real-time system has to complete program executions in predetermined time, the RTOS simulator that can estimate the execution time is yeW useful in the development phase. In this study, we develop a machine instruction-level RTOS simulator that is able to estimate execution time of application programs on a target hardware, and prove its functionality and accuracy by using test .programs.

• Proceedings of the KIEE Conference
• /
• 2000.07d
• /
• pp.2605-2607
• /
• 2000

This paper represents the construction of a PLC simulator for the level control of water and the speed control of the water cask. The level and speed processes are automatically operated by the PLC. The simulator system consists of PLC, program loader and control penal. The digital input and output units make the valves of the water cask the On or Off state. The analog input and output units control the level of water and the speed of the water cask. A LD program is used in the control language of PLC.

• The Transactions of the Korea Information Processing Society
• /
• v.2 no.4
• /
• pp.603-610
• /
• 1995

In this paper, we present a highly efficient simulation package which supports simulation from functional level to gate level. The package consists of a set of front-end tools, a logic simulator, named HSIM(Highly efficient logic SIMulator), and an waveform analyzer. The front-end tools include a netlist compiler, functional primitive compiler and behavioral compiler. Key feature of developed simulator is that the compiled behavioral models written in C language are directly executed in the simulation engine using incremental loader. By doing so, we achieved significant speed up as compared with the interpretive functional simulator. Experimental results show that HSIM runs about 55% faster than traditional unit-delay event-driven interpretive simulator.

• Journal of the Korean Society for Precision Engineering
• /
• v.32 no.9
• /
• pp.825-831
• /
• 2015

In this paper, capture motion and visual information from a virtual reality luge simulator to analyze muscular activity in the lower limbs. The Luge Simulator consists of a motion platform with a pneumatic module for weight distribution. We recruited luge athletes and healthy subjects and made real-time surface EMG measurements to estimate the muscular activity in the lower limbs according to the motion protocol of a simulator, and a test was conducted for each subject. The results indicated that the rectus femoris had the highest muscular activity according to the level of the slope and velocity of the luge. The soleus muscle showed a high level of activity during a turn in the luge according to the direction. We found that the development of a virtual reality sports simulator based on physical reaction results could bring positive effects to optimize reality and human cenesthesia.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.3
• /
• pp.1123-1130
• /
• 2018

Voltage stabilization is an essential component of power quality in low voltage DC (LVDC) microgrid. The microgrid demands the interconnection of a number of small distributed power resources, including variable renewable generators. Therefore, the voltage can be maintained in a stable manner through the control of these distributed generators. In this study, we did research on the new advanced operating method for a photovoltaic (PV) simulator in order to achieve interconnection to a bipolar LVDC microgrid. The validity of this voltage stabilization method, using the distributed generators, is experimentally verified. The test LVDC microgrid is configured by connecting the developed PV simulator and DC load, DC line, and AC/DC rectifier for connecting the main AC grid. The new advanced control method is applied to the developed PV simulator for the bipolar LVDC grid in order to stabilize the gird voltage. Using simulation results, the stabilization of the grid voltage by PV simulator using the proposed control method is confirmed the through the simulation results in various operation scenarios.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.12
• /
• pp.57-64
• /
• 2008

In this paper, we propose a system-level simulator for the performance analysis of a Solid-State Disk (SSD) in PC environment by using TLM (Transaction Level Modeling) method. Our method provides quantitative analysis for a variety of architectural choices of PC system as well as SSD. Also, it drastically reduces the analysis time compared to the conventional RTL (Register Transfer Level) modeling method. To show the effectiveness of the proposed simulator, we performed several explorations of PC architecture as well as SSD. More specifically, we measured the performance impact of the hit rate of a cache buffer which temporarily stores the data from PC. Also, we analyzed the performance variation of SSD for various NAND Flash memories which show different response time with our simulator. These experimental results show that our simulator can be effectively utilized for the architecture exploration of SSD as well as PC.

• Proceedings of the KSR Conference
• /
• 2005.05a
• /
• pp.175-180
• /
• 2005

As the high performance computer system increases, improving of reality and usefulness causes the virtual environment of simulator to be used widely as training and assessment tool. Although some domestic companies have developed train driving simulators since about mid of 1990s, accumulation of technology and experience is not yet sufficient compared to foreign makers. This paper describes system composition, training and assessment regimes for high level train driving simulator. When the subsystems are designed, comprehension of train system is emphasized and the functions that simulator should provide are discussed.