• 산업경영시스템학회지
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• 제28권3호
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• pp.149-155
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• 2005

In this paper, we optimize simulation model of a manufacturing system using the real-coded genetic algorithm. Because the manufacturing system expressed by simulation model has stochastic process, the objective functions such as the throughput of a manufacturing system or the resource utilization are not optimized by simulation itself. So, in order to solve it, we apply optimization methods such as a genetic algorithm to simulation method. Especially, the genetic algorithm is known to more effective method than other methods to find global optimum, because the genetic algorithm uses entity pools to find the optimum. In this study, therefore, we apply the real-coded genetic algorithm to simulation optimization of a manufacturing system, which is known to more effective method than the binary-coded genetic algorithm when we optimize the constraint problems. We use the reproduction operator of the applied real-coded genetic algorithm as technique of the remainder stochastic sample with replacement and the crossover operator as the technique of simple crossover. Also, we use the mutation operator as the technique of the dynamic mutation that configures the searching area with generations.

• 한국시뮬레이션학회논문지
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• 제3권1호
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• pp.43-53
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• 1994

With remarkable progress of hardware technologies, multiprocessor systems equipped with thousands of processors will be available in near future. In order to increase the performance of these systems, many processor allocation algorithms have been proposed. However, few studies have been conducted in order to compare the performance of these algorithms. In this paper, simulation techniques are used in order to compare the performance of the processor allocation algorithms proved to be useful. These are: an algorithm using equipartion, an algorithm using average parallelism, an algorithm using execution signatures, and an algorithm using the number of tasks in a task precedence graph. Simulation shows that the algorithm using execution signatures performs best while the algorithm using average parallelism performs worst with small allocated processors. Surprisingly, the algorithm using equipartition performs well despite the fact that it has smallest overhead. Overall, it can be recommended that the algorithm using equipartition be used without any execution history and that the algorithm using execution signatures be used with some execution history.

• 한국시뮬레이션학회논문지
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• 제6권1호
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• pp.1-13
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• 1997

In this paper, we present a partitioning algorithm for distributed simulation of DEVS (Discrete Event System Specification) models. To preserve concurrency inherent in models, the proposed algorithm utilizes the structural information of models. Through benchmark simulation experiments, we show that the proposed algorithm can generate good partitions.

• 전자공학회논문지B
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• 제32B권6호
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• pp.849-861
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• 1995

In this paper, a new trace driven simulation algorithm is proposed to evaluate the bus traffic and the miss ration of the various sector cache memories, which have various sub-block sizes and block sizes and associativities and number of sets, with a single pass through an address trace. Trace-driven simulaton is usually used as a method for performance evaluation of sector cache memories, but it spends a lot of simulation time for simulating the diverse cache configurations with a long address trace. The proposed algorithm shortens the simulation time by evaluating the performance of the various sector cache configurations. which have various sub-block sizes and block sizes and associativities and number of sets , with a single pass through an address trace. Our simulation results show that the run times of the proposed simulation algorithm can be considerably reduced than those of existing simulation algorithms, when the proposed algorithm is miplemented in C language and the address traces obtained from the various sample programs are used as a input of trace-driven simulation.

• 동력기계공학회지
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• 제6권3호
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• pp.64-70
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• 2002

A fast decoupled algorithm for time domain simulation of power electronics circuits is presented. The circuits can be arbitrarily configured and can incorporate feedback amplifier circuits. This simulation algorithm is performed for the input series output parallel connected 2 switch forward converter. Steady state and large signal transient responses due to a step load change are simulated. The simulation results are verified through experiments.

• 대한산업공학회지
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• 제32권1호
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• pp.9-17
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• 2006

This paper deals with a discrete simulation optimization method for designing a complex probabilistic discrete event simulation. The developed algorithm uses the configuration algorithm that can change decision variables and the stopping algorithm that can end simulation in order to satisfy the given objective value during single run. It tries to estimate an auto-regressive model for evaluating correctly the objective function obtained by a small amount of output data. We apply the proposed algorithm to M/M/s model, (s, S) inventory model, and known-function problem. The proposed algorithm can't always guarantee the optimal solution but the method gives an approximate feasible solution in a relatively short time period. We, therefore, show the proposed algorithm can be used as an initial feasible solution of existing optimization methods that need multiple simulation run to search an optimal solution.

• 한국시뮬레이션학회논문지
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• 제11권2호
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• pp.67-75
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• 2002

This paper proposes a parallel simulation algorithm for bounded Petri nets in a single processor, which exploits the SIMD(Single Instruction Multiple Data)-type parallelism. The proposed algorithm is based on a data packing scheme which packs multiple bytes data in a single register, thereby being manipulated simultaneously. The parallelism can reduce simulation time of bounded Petri nets in a single processor environment. The effectiveness of the algorithm is demonstrated by presenting speed-up of simulation time for two bounded Petri nets.

• 한국통신학회논문지
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• 제21권6호
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• pp.1533-1545
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• 1996

In this paper, the design and implementation of echo canceller with new variable step size algorithm is discussed. The method used in the new algorithm is to periodically adopt the test function which helps an optimal coefficient tracking. This algorithm outperforms LMS and VS algorithms in convergence speed and steady state error. As the period of test function is decreased, the speed of convergence is improved, but the number of calculation is increased, then the trade off between these parameters must be considered. Simulation results show new algorithm outperforms LMS and VS algorithms in convergence rate. For the design of hardware, circuit is designed with VHDL, and synthesized with Act1 withc is a FPGA library of ActelTM in use of synovation of InterGraph$^{TM}$. Verification of the synthesized circuit is carried out with simulator DLAB. The circuit based on the algorithm which is suggested in this paper calculated 7 radix places of inary number. A simulation data for the verification is based on the data of algorithm simulation. When the same input data is applied to the both simulation, output results of circuit simulation had slight difference in compare with that of algorithm simulation. The number of used gate is about 5,500 and We have 5.53MHz in maximum frequency.y.

• 한국시뮬레이션학회논문지
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• 제4권2호
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• pp.79-92
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• 1995

In this paper we present an efficient parallel simulation algorithm in recursive feedforward network(RFN) which can reduce the simulation delay while decreasing the number of null messages compared to the previous result. As a preprocessing step, we first determine the group and type of each oupput channel for the nodes using DFS(Depth First Search) algorithm, and show that the number of null messages as well as the simulation scheme. By the new scheme we decide if null messages are sent to the output channels or not according to the group to which it belongs.

• 한국시뮬레이션학회논문지
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• 제3권1호
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• pp.89-98
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• 1994

In this paper, a criteria for selecting an appropriate load redistribution algorithm is devised so that a fault-tolerance distributed system can operte at its optimal efficience. To present the guideline for selecting redistributing algorithms, simulation models of fault-tolerant system including redistribution algorithms are developed using SLAM II. The job arrival rate, service rate, failure and repair rate of nodes, and communication delay time due to load migration are used as parameters of simulation. The result of simulation shows that the job arrival rate and the failure rate of nodes are not deciding factors in affecting the relative efficiency of algorithms. Algorithm B shows relatively a consistent performance under various environments, although its performance is between those of other algorithms. If the communication delay time is longer than average job processing time, the performance of algorithm B is better than others. If the repair rate is relatively small or communication delay time is longer than service time, algorithm A leads to good performance. But in opposite environments, algorithm C is superior to other algorithms.