• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.1-10
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• 2000

A rigorous modeling of ultra-low energy implantation is becoming increasingly more important as devices shrink to deep submicron dimensions. In this paper, we have developed an efficient three-dimensional Monte Carlo ion implantation model based on a modified Binary Collision Approximation(BCA). To this purpose, the modified electronic stopping model and the multi-body collision model have been taken into account in this simulator. The dopant and damage profiles show very good agreement with SIMS(Secondary Ion Mass Spectroscopy) data and RBS(Rutherford Backscattering Spectroscopy) data, respectively. Moreover, the ion distribution replica method has been implemented into the model to get a computational efficiency in a 3D simulation, and we have calculated the 3D Monte Carlo simulation into the topographically complex structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.262-271
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• 2011

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.

• Journal of the Korean Ceramic Society
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• v.50 no.6
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• pp.364-371
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• 2013

The sintering behavior of monolithic SiC is examined using the binary sintering additive of $Al_2O_3$-rare earth oxide ($RE_2O_3$, where RE = Sc, Nd, Dy, Ho, or Yb). Through hot pressing at 20 MPa and $1750^{\circ}C$ for 1 h in an Ar atmosphere for 52 nm fine ${\beta}$-SiC powder added with 5 wt% sintering additive, a SiC density of > 97% is achieved, which indicates the effectiveness of $Al_2O_3-RE_2O_3$ system as a sintering of additive for SiC. Based on this result, 7 wt% of $Al_2O_3-Sc_2O_3$ is tested as an additive system for the fabrication of a continuous SiC fiber-reinforced SiC-matrix composite ($SiC_f$/SiC). Electrophoretic deposition combined with the application of ultrasonic pulses is used to efficiently infiltrate the matrix phase into the voids of $Tyranno^{TM}$-SA3 fabric. After hot pressing, a composite density of > 97% is obtained, along with a maximum flexural strength of 443 MPa.

• Journal of IKEEE
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• v.24 no.1
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• pp.170-177
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• 2020

This paper presents an open-fault tolerance control method for active neutral point clamped (ANPC) inverter with high frequency/low frequency (HF/LF) modulation. By applying the ANPC inverter with SiC MOSFETs and Si IGBTs, the system efficiency and performance can be improved compared to a Si-based inverter. HF/LF modulation is used for a megawatt-scale inverter to minimize the commutation loop. The open-switch failure in megawatt-scale inverter causes severe damage to load and huge expenses when the inverter has been shut-down. The proposed tolerance control of open-switch failure provides continuous operation and improved reliability to the ANPC inverter. The effectiveness of the proposed fault tolerance control is verified by simulation results.

• Journal of the Korean Society of Safety
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• v.14 no.1
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• pp.101-107
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• 1999

$TiO_2$ and $xTiO_2-ySiO_2$ system photocatalysts were developed by sol-gel method based on the change of production parameters, and their structure of crystallization and the specific surface area was measured. Considering the efficiency of the ethanol decomposition using the catalyst, the conclusion was made as follows: 1) By means of X-ray analysis of $TiO_2$ powder that is obtained from water and Titanium alkoxide with various molar ratios, it is shown that structure of crystallization is a dominating structure and, on the other hand, the crystallization of rutile also partly exists. The specific surface area is at its maximum value at R=6, which is the molar ratio of water vs. alkoxide, whereas its value goes down as the molar ratio increases. In the reaction of using $TiO_2$ catalyst, the ethanol is decomposed into the extent of 15 ~30% in an hour and three hours are necessitated for 70% decomposition. 2) $TiO_2/SiO_2$ powder is developed from Titanium and Silicon alkoxide by a hetero-condensation process. The increase of SiO$_2$ contents causes the decrease of the degree of crystallization of the gel, whereas the specific surface area preferentially increases. In the decomposition reaction of the ethanol, the decomposition efficiency represents 25~60% in an hour. It is, however, examined that the efficiency inactively increases corresponding to the duration of reaction time. It is shown that more than 90% of ethanol is decomposed when reaction time is about three hours and the efficiency illustrates the maximum value for 60-$TiO_2/4O-SiO_2$ catalyst.

• Composites Research
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• v.12 no.2
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• pp.70-81
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• 1999

Resin transfer molding(RTM) as a composite manufacturing process is currently of great interest in the aerospace industry requiring high performance composite parts. In this study, an analysis of mold filling in the RTM process was carried out by numerical simulation using finite element/control volume technique. Experimental work for the visualization of resin flow through fibrous preform was also conducted in order to quantitatively measure the permeabilities of the fiber mats and to evaluate the validity of the developed numerical code. The different types of fiber mats and silicon oils were selected as reinforcements and resin materials, respectively. The effects of fibrous preform structure, mold geometry, and preplaced insert on the flow front patterns during mold filling were examined by integrating the model predictions and experimental results. The flow fronts predicted by numerical simulation were in good agreement with those observed experimentally. However, according to the regions of the mold, some deviations between predicted and observed flow fronts could be found because of non-uniform fiber volume fraction. Weldline locations for the resin flow through round insert preplaced in the mold could be qualitatively deduced based on predicted flow fronts.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.11-19
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• 2003

A micro sensor array with 4 discrete sensors integrated on a microhotplate was developed for identifying the kinds and quantities of explosive gases. The sensor array consisited of four tin oxide-based thin films with the high and broad sensitivity to the tested explosive gases and uniform thermal distribution on the plate. The microhotplate, using silicon substrate with N/O/N membrane, dangling in air by Al bonding wires, and controlling the thickness by chemical mechanical process (CMP), has been designed and fabricated. By employing the sensitivity signal of the sensor array at 40$0^{\circ}C$, we could reliably classily the kinds and quantities of the explosive gases like butan, propane, LPG, and carbon monoxide within the range of threshold limit values (TLVs), employing principal component analysis (PCA).

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.