• Title/Summary/Keyword: Silicon-Based

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(Various Electionic system Applications by Using Silicon-based Thin Films) (실리콘계 박막을 이용한 다양한 전자시스템 응용)

  • 이준신
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.186.2-189
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    • 2001
  • 요실리콘을 기반으로 하는 박막은 반도체 재료로 Si, Si:Ge, SiC등이 사용되고있으며, 절연박막재료로 SiN, SiOxNy, SiOx 등이 있다. 이들 재료는 국내 반도체 산업의 핵심위치에 있는 물질이다. 한국 산업의 근간이라 할 수 있는 메모리분야에 적용될 뿐만 아니라 TFT-LCD, 태양전지, 각종 센서, X-ray 사진 촬영기 개발에도 응용되고 있다. 본 논문에서는 Silicon-based 박막의 제조기법과 그에 따른 다양한 실리콘 박막 실리콘 트랜지스터를 이용한 능동형 액정과 유기발광 화소제어 활용, 센서 응용 부분에서 태양전지, X-ray 촬영기활용 분야에서 기술현황 시장분석을 통해 차세대 연구개발의 방향을 제시하고자 한다. 현재 국내에서 실리콘 박막의 가장 큰 응용 분야는 메모리 소자의 평판디스플레이의 TFT-LCD 시장이다. 그러나 실리콘 박막으로 가능한 응용분야는 아직 산업계에서 열매를 맺지 못한 분야가 더 많고 실제로 적용할 수 있는 분야의 다양함을 본 논문을 통해 소개한다.

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Silicon Nitride Cantilever Array Integrated with Si Heaters and Piezoelectric Sensors for Probe-based Data Storage

  • Nam Hyo-Jin;Kim Young-Sik;Lee Caroline Sunyong;Jin Won-Hyeog;Jang Seong-Soo;Cho Il-Joo;Bu Jong-Uk
    • Transactions of the Society of Information Storage Systems
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    • v.1 no.1
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    • pp.73-77
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    • 2005
  • In this paper, a new silicon nitride cantilever integrated with silicon heater and piezoelectric sensor has been firstly developed to improve the uniformity of the initial bending and the mechanical stability of the cantilever array for thermo-piezoelectric SPM(scanning probe microscopy) -based data storages. This nitride cantilever shows thickness uniformity less than $2\%$. Data bits of 40 nm in diameter were recorded on PMMA film. The sensitivity of the piezoelectric sensor was 0.615 fC/nm after poling the PZT layer. For high speed operation, 128${\times}$128 probe array was developed.

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Visible Wavelength Photonic Insulator for Enhancing LED Light Emission

  • Ryoo, Kwangki;Lee, Jeong Bong
    • Journal of information and communication convergence engineering
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    • v.13 no.1
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    • pp.50-55
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    • 2015
  • We report design and simulation of a two-dimensional (2D) silicon-based nanophotonic crystal as an optical insulator to enhance the light emission efficiency of light-emitting diodes (LEDs). The device was designed in a manner that a triangular array silicon photonic crystal light insulator has a square trench in the middle where LED can be placed. By varying the normalized radius in the range of 0.3-0.5 using plane wave expansion method (PWEM), we found that the normalized radius of 0.45 creates a large band gap for transverse electric (TE) polarization. Subsequently a series of light propagation simulation were carried out using 2D and three-dimensional (3D) finite-difference time-domain (FDTD). The designed silicon-based light insulator device shows optical characteristics of a region in which light propagation was forbidden in the horizontal plane for TE light with most of the visible light spectrum in the wavelength range of 450 nm to 600 nm.

Compact and Temperature Independent Electro-optic Switch Based on Slotted Silicon Photonic Crystal Directional Coupler

  • Aghababaeian, Hassan;Vadjed-Samiei, Mohammad-Hashem
    • Journal of the Optical Society of Korea
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    • v.16 no.3
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    • pp.282-287
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    • 2012
  • In this paper, we have proposed a principle to design a compact and temperature independent electro-optic switch based on a slotted photonic crystal directional coupler (SPCDC). Infiltration of the slotted silicon photonic crystal with polymer enhances the slow light and decreases the switching length, whereas the different signs of thermo-optic coefficients of the polymer and silicon make the proposed switch stable within $25^{\circ}C$ to $85^{\circ}C$ temperature range. The SPCDC structure is modified to increase poling efficiency of the polymer in the slot and to flatten the dispersion diagram of the even mode to minimize the switching length.

Optimal Parameter Selection of Near-Infrared Optics Based Design of Experiment for Silicon Wafer in Solar Cell (태양전지 실리콘 웨이퍼를 위한 실험계획법 기반 근적외선 광학계의 최적조건 선정)

  • Seo, Hyoung Jun;Kim, Gyung Bum
    • Journal of the Semiconductor & Display Technology
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    • v.12 no.3
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    • pp.29-34
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    • 2013
  • Solar cell has been considered as renewable green energy. Its silicon wafer thickness is thinner due to manufacturing cost and accordingly micro cracks is often generated in the process. Micro cracks result in bad quality of solar cell, and so their accurate and reliable detection is required. In this paper, near-infrared optics system is newly designed based on the analysis of near-infrared transmittance characteristics and its important parameters are optimally selected using the design of experiment for micro crack detection in solar cell wafer. The performance of the proposed method is verified using several experiments.

Optical Characterization of Smart Dust Based on Photonic Crystals and Its Sensing Applications

  • Kim, Sung Gi
    • Journal of Integrative Natural Science
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    • v.4 no.1
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    • pp.7-10
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    • 2011
  • Various types of smart dust based on photonic crystal exhibiting unique reflectivity were successfully obtained by an electrochemical etching of silicon wafer using square wave currents. Smart dust containing Bragg structure obtained from the sonication of DBR porous silicon film in solution retained its optical reflectivity. Field emission scanning electron micrograph (FE-SEM) was used to measure the size of optically encoded smart dust and its size can be tuned from few hundred nanometers to few microns depending on the duration of sonication. Optical characteristics of smart dust were used to investigate a possible applications such as chemical sensors.

Performance Comparison of Two Types of Silicon Avalanche Photodetectors Based on N-well/P-substrate and P+/N-well Junctions Fabricated With Standard CMOS Technology

  • Lee, Myung-Jae;Choi, Woo-Young
    • Journal of the Optical Society of Korea
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    • v.15 no.1
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    • pp.1-3
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    • 2011
  • We characterize and analyze silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth of CMOS-APDs based on two types of PN junctions, N-well/P-substrate and $P^+$/N-well junctions, are compared and analyzed. It is demonstrated that the CMOS-APD using the $P^+$/N-well junction has higher responsivity as well as higher photodetection bandwidth than N-well/P-substrate. In addition, the important factors influencing CMOS-APD performance are clarified from this investigation.

Effect of the Neutral Beam Energy on Low Temperature Silicon Oxide Thin Film Grown by Neutral Beam Assisted Chemical Vapor Deposition

  • So, Hyun-Wook;Lee, Dong-Hyeok;Jang, Jin-Nyoung;Hong, Mun-Pyo
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.253-253
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    • 2012
  • Low temperature SiOx film process has being required for both silicon and oxide (IGZO) based low temperature thin film transistor (TFT) for application of flexible display. In recent decades, from low density and high pressure such as capacitively coupled plasma (CCP) type plasma enhanced chemical vapor deposition (PECVD) to the high density plasma and low pressure such as inductively coupled plasma (ICP) and electron cyclotron resonance (ECR) have been used to researching to obtain high quality silicon oxide (SiOx) thin film at low temperature. However, these plasma deposition devices have limitation of controllability of process condition because process parameters of plasma deposition such as RF power, working pressure and gas ratio influence each other on plasma conditions which non-leanly influence depositing thin film. In compared to these plasma deposition devices, neutral beam assisted chemical vapor deposition (NBaCVD) has advantage of independence of control parameters. The energy of neutral beam (NB) can be controlled independently of other process conditions. In this manner, we obtained NB dependent high crystallized intrinsic and doped silicon thin film at low temperature in our another papers. We examine the properties of the low temperature processed silicon oxide thin films which are fabricated by the NBaCVD. NBaCVD deposition system consists of the internal inductively coupled plasma (ICP) antenna and the reflector. Internal ICP antenna generates high density plasma and reflector generates NB by auger recombination of ions at the surface of metal reflector. During deposition of silicon oxide thin film by using the NBaCVD process with a tungsten reflector, the energetic Neutral Beam (NB) that controlled by the reflector bias believed to help surface reaction. Electrical and structural properties of the silicon oxide are changed by the reflector bias, effectively. We measured the breakdown field and structure property of the Si oxide thin film by analysis of I-V, C-V and FTIR measurement.

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Study on Ductile Machining Technology for Manufacturing Nano-Patterns on Single Crystal Silicon through Quantitative Analysis of Thrust Force (배분력의 정량적인 분석을 통한 단결정실리콘의 나노패턴 연성가공법 연구)

  • Choi, Dae-Hee;Jeon, Eun-chae;Yoon, Min-Ah;Kim, Kwang-Seop;Je, Tae-Jin;Jeong, Jun-Ho
    • Journal of the Korean Society for Precision Engineering
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    • v.33 no.1
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    • pp.11-16
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    • 2016
  • Lithography techniques are generally used to manufacture nano-patterns on silicon, however, it is difficult to make a V-shaped pattern using these techniques. Although silicon is a brittle material, it can be treated as a ductile material if mechanically machined at extremely low force scale. The manufacturing technique of nano-patterns on single crystal silicon using a mechanical method was developed in this study. First, the linear pattern was machined on the silicon with increasing thrust force. Then, the correlation between measured cutting force and machined pattern was analyzed. Based on the analysis, the critical thrust force was quantitatively determined, and then the silicon was machined at a force lower than the critical thrust force. The machined pattern was observed using SEM and AFM to check for the occurrence of brittle fractures. Finally, the sharp V-shaped nano-pattern was manufactured on the single crystal silicon.

An Analysis on Electrical Double Layers at the Silicon Semiconductor Interfaces Using the Zeta Potential (Zeta전위에 의한 Silicon 반도체 계면의 전기이중층 해석)

  • Chun, Jang-Ho
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.2
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    • pp.242-247
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    • 1987
  • Electrophysical phenomena at the silicon semiconductor-electrolyte solution interfaces were analyzed based on the zeta potential of the electrical double layer and microelectrophoresis. The suspensions were composed of the p or n-type silicon particles suspended in the KCI or pH buffer solutions. The approximate diameter of the prepared and sampled sioicon semiconductor pardticles was 1.5\ulcorner. The sign of the zeta poetntials of the p and n-type silicon particles in the KCl and pH buffer solution was positive. A range of electrophoretic mobilities of the p and n-type silicons in the KCl solutions was 5.5-8.9x10**-4 cm\ulcornerV-sec and 4.2-7.9x10**-4cm\ulcornerV-sec, respectively. The range of zeta potentials corresponding to the electrophoretic mobilities is 70.4-114.0mV nad 53.9-101.2mV, respectively. On the other hand, a range of electrophoretic mobilities of the p and n-type silicons in the pH buffer solutions was 1.1x10**-4-2.2x10**-3cm\ulcornerV-sec and 0-2.1x10**-3cm\ulcornerV-sec, respectively. The range of zeta potentials corresponding to the electrophoretic mobilities is 14.1-281.6mV and 0-268.8mV, respectively. The zeta potentials and electrical double layers of the doped silicon semiconductors are decisively influenced by the positively charged ions in the solutions. The maximum values of the zeta potentials in the KCl solutions appeared at a concentration of about 10-\ulcorner. The isoelectric point of the n-type silicon semiconductors appeared at about a pH 7. The effect of the space charge of the doped silicon semiconductors can be neglected compare with the effect of the surface charge.

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