• Journal of the Optical Society of Korea
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• 제14권4호
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• pp.290-297
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• 2010

The paper reviews progress and future prospects of two kinds of planar waveguide devices; they are (a) silica and silicon photonics multi/demultiplexers for communications and signal processing applications, and (b) a novel waveguide spectrometer based on Fourier transform spectroscopy for sensing applications.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 추계학술대회 논문집
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• pp.729-730
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• 2010

• 태양에너지
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• 제8권2호
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• pp.73-76
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• 1988

Thick films based on the mature crystalline silicon technology are expected to exhibit eversmaller cost reduction. The thin-film-based technology is, however, expected to exhibit a much sharper drop in cost as it develops. In this report, technology and recent R & D of thin film solar cell, such as amorphous silicon, cadnium telluride, copper indium diselenide and gallium arsenide, are described. Perspectives of world photovoltaic market and solar cell price are also described.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• 산업공학
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• 제18권3호
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• pp.234-246
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• 2005

A silicon wafer is a highly customized product made to the individual order varying its electrical and physical characteristics. Therefore, it has distinctive supply chain structure that is different from highly standardized commodity product. For high-volume/high-standardization product, it is general that a main stream of information flow initiated by the production planning of the manufacturers is usually directed to push both ways in a supply chain: upstream to the suppliers and downstream to the customers. Contrastingly, for low-volume/high-customization product, the information flow triggered by the fluctuating customer demand usually propagates upward to the suppliers through the manufacturers. Furthermore, for R &D based hi-technology product like silicon wafer, the interactive information feedback mechanism between manufacturer and customer, which is essential to the new product development process, is to be embedded in the supply chain. This article is a case study of supply chain management system of LG Siltron, a major Korean silicon wafer manufacturer. The SCM system entails special information structure fitting well typical high-variety/high-customization product, and also gives application possibilities to the R&D based high-technology product made to the individual customer order.

• 한국전기전자재료학회논문지
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• 제17권6호
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• pp.592-597
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• 2004

Porous silicon(PS) has received much attention as a sensitive material of chemical sensors because of its large internal surface area. In this work, we fabricated gas-sensing devices based on the porous silicon layer which could be applicable to the measurement of blood alcohol content(BAC), and estimated their electrical properties. The structure of the sensor is similar to an MIS (metal-insulator-semiconductor) diode and consists of thin Au/oxidized PS/PS/p-Si/Al, where the p-Si substrate is etched anisotropically to reduce the thickness. We measured C-V curves from two types of the samples with the PS layer treated by the different anodization current density of 60 or 100 mA/cm$^2$, in order to compare the sensitivity. As a result, the magnitude and variation of capacitances from the devices with the PS formed under the current density of 100 mA/cm$^2$ were found to be more detectable due to the larger internal surface.

• 한국전기전자재료학회논문지
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• 제17권11호
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• pp.1218-1223
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• 2004

Porous silicon materials have been shown to have bright prospects for applications in light emitting, solar cell, as well as light- and chemical-sensing devices. In this report, structures of porous silicon prepared by anodic etching in HF-based solution with various etching times were studied in detail by Atomic Force Microscopy and Small Angle X -ray Scattering technique using the high energy beam line at Pohang Light Source in Korea. The results showed the coexistence of the various pores with nanometer and submicrometer scales. For nanameter size pores, the mixed ones with two different shapes were identified: the larger ones in cylindrical shape and the smaller ones in spherical shape. Volume fractions of the cylindrical and the spherical pores were about equal and remained unchanged at all etching times investigated. On the whole uniform values of the specific surface area and of the size parameters of the pores were observed except for the larger specific surface area for the sample with the short etching time. The results implies that etching process causes the inner surfaces to become smoother while new pores are being generated. In all SAXS data at large Q vectors, Porod slope of -4 was observed, which supports the fact that the pores have smooth surfaces.

• 한국정밀공학회지
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• 제23권8호
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• pp.39-46
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• 2006

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin mask layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The mask layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.147-152
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• 2016

In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

• 한국정밀공학회지
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• 제20권5호
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• pp.189-195
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• 2003

Atomic Force Microscope (AFM) has been widely used in micro/nano-scale studies and applications for. the last few decade. In this work, wear characteristics of silicon-based AFM tip was investigated. AFM tip shape was observed using a high resolution SEM and the wear coefficient was approximately calculated based on Archard's wear equation. It was shown that the wear coefficient of silicon and silicon nitride were in the range of ${10}^{-1}$~${10}^{-3}$ and ${10}^{-3}$~${10}^{-4}$, respectively. Also, the effect of relative humidity and sliding distance on adhesion-induced tip wear was discussed. It was found that the tip wear has more severe for harder test materials. Finally, the probable wear mechanism was analyzed from the adhesive and abrasive interaction point of view.