• 한국재료학회:학술대회논문집
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• 한국재료학회 2002년도 추계학술발표강연 및 논문개요집
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• pp.90-90
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• 2002

• 한국진공학회지
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• 제13권1호
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• pp.29-33
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• 2004

본 논문에서는 RF 마그네트론 스퍼터링법으로 비정질 실리콘을 증착하여 진공분위기에서 엑시머 레이저 어닐링을 이용하여 플라스틱 기판위에 극저온 다결정 실리콘 박막(＜$150^{\circ}C$)을 형성하였다. 비정질 실리콘 박막은 $120^{\circ}C$에서 Ar/He 혼합가스로 증착하였으며, Rutherford Backscattering Spectrometry로 측정한 박막내 아르곤 함량은 2% 이하였다. 에너지 밀도 320mJ/$\textrm{cm}^2$일 때 다결정 실리콘의 결정화도는 62%, Root-Mean-Square roughness는 267$\AA$를 나타내었다. 엑시머 레이저 결정화 후 결정립의 크기는 50nm에서 100nm 정도를 나타내었다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

• 전자통신동향분석
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• 제5권1호
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2005년도 춘계학술대회 논문집
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• pp.395-400
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• 2005

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin damaged layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The damaged layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• 반도체디스플레이기술학회지
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• 제14권4호
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• pp.45-49
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• 2015

Using a combined CVD and ALD equipment system, multi-layer quantum well structures of $Al_2O_3/a-Si/Al_2O_3$ were fabricated on silicon Schottky junction devices and implemented to quantum well solar cells, in which the 1~1.5 nm thicknesses of the aluminum oxide films and the a-Si thin film layers were deposited at $300^{\circ}C$ and $450^{\circ}C$, respectively. Fabricated solar cell was operated by tunneling phenomena through the inserted quantum well structure being generated electrons on the silicon surface. Efficiency of the fabricated solar cell inserted with multi-quantum well of 41 layers has been increased by about 10 times that of the solar cell of pure Schottky junction solar cell.

• 한국전기전자재료학회논문지
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• 제17권6호
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• pp.592-597
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• 2004

Porous silicon(PS) has received much attention as a sensitive material of chemical sensors because of its large internal surface area. In this work, we fabricated gas-sensing devices based on the porous silicon layer which could be applicable to the measurement of blood alcohol content(BAC), and estimated their electrical properties. The structure of the sensor is similar to an MIS (metal-insulator-semiconductor) diode and consists of thin Au/oxidized PS/PS/p-Si/Al, where the p-Si substrate is etched anisotropically to reduce the thickness. We measured C-V curves from two types of the samples with the PS layer treated by the different anodization current density of 60 or 100 mA/cm$^2$, in order to compare the sensitivity. As a result, the magnitude and variation of capacitances from the devices with the PS formed under the current density of 100 mA/cm$^2$ were found to be more detectable due to the larger internal surface.

• 한국정밀공학회지
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• 제23권8호
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• pp.39-46
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• 2006

Nano-scale fabrication of silicon substrate based on the use of atomic force microscopy (AFM) was demonstrated. A specially designed cantilever with diamond tip, allowing the formation of damaged layer on silicon substrate by a simple scratching process, has been applied instead of conventional silicon cantilever for scanning. A thin mask layer forms in the substrate at the diamond tip-sample junction along scanning path of the tip. The mask layer withstands against wet chemical etching in aqueous KOH solution. Diamond tip acts as a patterning tool like mask film for lithography process. Hence these sequential processes, called tribo-nanolithography, TNL, can fabricate 2D or 3D micro structures in nanometer range. This study demonstrates the novel fabrication processes of the micro cantilever and diamond tip as a tool for TNL using micro-patterning, wet chemical etching and CVD. The developed TNL tools show outstanding machinability against single crystal silicon wafer. Hence, they are expected to have a possibility for industrial applications as a micro-to-nano machining tool.

• 센서학회지
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• 제16권2호
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• pp.85-90
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• 2007

This paper presents the growth conditions and characteristics of polycrystalline 3C-SiC (silicon carbide) thin films for M/NEMS applications related to harsh environments. The growth of the 3C-SiC thin film on the oxided Si wafers was carried out by APCVD using HMDS (hexamethyildisilane: $Si_{2}(CH_{3})_{6})$ precursor. Each samples were analyzed by XRD (X-ray diffraction), FT-IR (fourier transformation infrared spectroscopy), RHEED (reflection high energy electron diffraction), GDS (glow discharge spectrometer), XPS (X-ray photoelectron spectroscopy), SEM (scanning electron microscope) and TEM (tunneling electro microscope). Moreover, the electrical properties of the grown 3C-SiC thin film were evaluated by Hall effect. From these results, the grown 3C-SiC thin film is very good crystalline quality, surface like mirror and low defect. Therefore, the 3C-SiC thin film is suitable for extreme environment, Bio and RF M/NEMS applications in conjunction with Si fabrication technology.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.467-470
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• 2004

Diamond-Like Carbon (DLC) thin film is a semiconductor with high mechanical hardness, low friction coefficient, high chemical inertness, and optical transparency. DLC thin films have widespread applications as protective coatings and solid lubricant coatings in areas such as Hard Disk Drive (HDD) and Micro-Electro-Mechanical-Systems (MEMS). In this work, the wear characteristics of DLC thin films deposited on silicon substrates using a DC-magnetron sputtering system were analyzed. The wear tracks were measured with an Atomic Force Microscope (AFM). To identify the sp2 and sp3 hybridization of carbon bonds and other bonds Raman spectroscopy was used. The structural information of DLC thin films was obtained with Fourier transform infrared spectroscopy and wear tests were conducted by using a micro-pin-on-reciprocator tester. Results showed that the wear characteristics were dependent on the sputtering conditions. The wear rate could be correlated with the bonding state of the DLC thin film.