• Journal of the Semiconductor & Display Technology
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• v.11 no.4
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• pp.19-23
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• 2012

We report microbolometer characteristic with n-type and p-type amorphous silicon thin film. The n-type and p-type amorphous silicon thin films were made by PECVD. The electrical properties of n-type and p-type a-Si:H thin films were investigated as a function of doping gas flow rate. The doping gas used $B_2H_6/Ar$ (1:9) and $PH_3/Ar$ (1:9). In general, the conductivity of doping a-Si:H thin films increased as doping gas increase but the conductivity of a-Si:H thin films decreased as the doping gas increase because doping gas concentration increase led to dilution gas (Ar) increase as the same time. We fabricated an amorphous silicon microbolometer using surface micromachining technology. The fabricated microbolometer had a negative TCR of 2.3%. The p-type microbolometer had responsivity of $5{\times}10^4V/W$ and high detectivity of $3{\times}10^8cm(Hz)^{1/2}/W$. The p-type microbolometer had more detectivity than n-type for less noise value.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.6
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• pp.433-439
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• 2011

Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.88-88
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• 2012

High efficiency thin film photovoltaic device technology is reviewed. At present market situation, the industrial players of thin film technologies have to confront the great recession and need to change their market strategies and find technical alternatives again. Most recent technology trends and technical or industrial progress for Silicon thin film and CIGS are introduced and common interests for high efficiency and reliability are discussed.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1455-1458
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• 2008

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) are fabricated on flexible organic polymer foil substrates. As-fabricated performance, electrical bias-stability at elevated temperatures, electrical response under mechanical flexing, and prolonged mechanical stability of the TFTs are studied. TFTs made on plastic at ultra low process temperatures of $150^{\circ}C$ show initial electrical performance like TFTs made on glass but large gate-bias stress instability. An abnormal saturation of the instability against operation temperature is observed.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.263-267
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• 2002

We are standing at the beginning of the industrialization of flexible thin-film transistor backplanes. An important group of candidates is based on silicon thin films made on metal or plastic foils. The main features of amorphous, nanocrystalline and microcrystalline silicon films for TFTs are summarized, and their compatibility with foil substrate materials is discussed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.3
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• pp.283-288
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• 2004

We have fabricated MIM capacitors for MMIC applications, with capacitances as high as 600pF/$\textrm{mm}^2$ and excellent electrical properties of the insulator layer. Silicon nitride thin film is the desirable material for MMIC capacitor fabrication. Standard MIM capacitance in MMIC is 300pF/$\textrm{mm}^2$ with an insulator layer thickness of more than 2000$\AA$. However, capacitors with thin insulator layers have breakdown voltages as low as 20V. We have deposited insulator layers by PECVD in our MIM structure with an air bridge between the top metal and the contact pad. The PECVD process was optimized for fabricating the desired capacitors to be used in MMIC. Silicon nitride(Si$_{x}$N$_{y}$) thin films of about 1000$\AA$ thick show capacitances of about 600pF/$\textrm{mm}^2$, and breakdown voltages above 70V at 100nA.A.A.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1065-1068
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• 2003

For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness( $T_{Si}$ + $T_{SiGe}$) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 % $I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of $I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• Journal of the Korean institute of surface engineering
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• v.23 no.4
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• pp.218-224
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• 1990

Silicon nitride thin(SiNx) is deposited onto 3 inch silicon wafor using ECR plasma apparatus. For the two different plasma extraction windows size, the thin films which were deposited by changing the SiH4/N2 gas fole at at 1.5mTorr without substrate heating are analyzed through the XPS and wlliposometer measurements. The very uniform and good quality silicon nitride thin film were obtained with the analyzed results of the deposited films, and particularly, ion temperature perpendicular to the magnetic filed was nearly same as the neutral gas temperature. The large amount of plasma loss in the transport process following magnetic field lines could be seen from the plasma emission intensity measurements.

• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.194-198
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• 2012

Crystalline silicon solar cell remains the major player in the photovoltaic marketplace with 80% of the market, despite the development of various thin film technologies. Silicon's excellent efficiency, stability, material abundance and low toxicity have helped to maintain its position of dominance. However, the cost of silicon materials remains a major barrier to reducing the cost of silicon photovoltaics. Using the crystalline silicon wafer with thinner thickness is the promising way for cost and material reduction in the solar cell production. However, the thinner the silicon wafer is, the worse bow phenomenon is induced. The bow phenomenon is observed when two or more layers of materials with different temperature expansion coefficiencies are in contact, in this case silicon and aluminum. In this paper, the solar cells were fabricated with different thicknesses of Al layer in order to reduce the bow phenomenon. With less amount of paste applications, we observed that the bow could be reduced by up to 40% of the largest value with 120 micron thickness of the wafer even though the conversion efficiency decrease by 0.5% occurred. Since the bowed wafers lead to unacceptable yield losses during the module construction, the reduction of bow is indispensable on thin crystalline silicon solar cell. In this work, we have studied on the counterbalance between the bow and conversion efficiency and also suggest the formation of enough back surface field (BSF) with thinner Al layer application.