• Journal of Advanced Marine Engineering and Technology
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• v.39 no.1
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• pp.45-51
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• 2015

In this paper, we study the RF characteristics of the short wavelength thin-film transmission line employing microstrip line (ML)/coplanar waveguide (CPW) composite structure on silicon substrate for application to RFIC (radio frequency integrated circuit). The thin-film transmission line employing ML/CPW composite structure showed a wavelength shorter than conventional transmission lines. Concretely, at 10 GHz, the wavelength of the transmission line employing ML/CPW composite structure was 6.26 mm, which was 60.5 % of the conventional coplanar waveguide. We also extracted the bandwidth characteristic of the transmission line employing ML/CPW composite structure using equivalent circuit analysis. The S parameter of the equivalent circuit showed a good agreement with measured result. According to the bandwidth extraction result, the cut-off frequency of thin-film transmission line employing ML/CPW composite structure was 377 GHz. Above results indicate that the transmission line employing ML/CPW composite structure can be effectively used for application to broadband and compact RFIC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.477-480
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• 2002

Si-O-C(-H) thin film with a tow dielectric constant were deposited on a P-type Si(100) substrate by an inductively coupled plasma chemical vapor deposition (ICPCVD). Bis-trimethylsilymethane (BTMSM, H$_{9}$C$_3$-Si-CH$_2$-Si-C$_3$H$_{9}$) and oxygen gas were used as Precursor. Hybrid type Si-O-C(-H) thin films with organic material have been generated many voids after annealing. Consequently, the Si-O-C(-H) films can be made a low dielectric material by the effect of void. The surface characterization of Si-O-C(-H) thin films were performed by SEM(scanning electron microscope). The characteristic analysis of Si-O-C(-H) thin films were performed by X-ray photoelectron spectroscopy (XPS).

• Korean Journal of Materials Research
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• v.2 no.5
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• pp.375-382
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• 1992

Molybdenum silicide films have been prepared by sputtering from a single composite MoS$i_2$ source on both P, B$F_2$respectively implanted (5${\times}10^{15}ions/cm^2$ single crystal and P implanted (5${\times}10^{15}ions/cm^2$) polycrystalline silicon substrates followed by rapid thermal annealing in the ambient of argon. The heat treatment temperatures have been varied in the range of 600-l20$0^{\circ}C$ for 20 seconds. The properties of Mo-silicide and the diffusion behaviors of dopant after the heat treatment are investigated using X-ray diffraction, scanning electron microscopy(SEM) , secondary ions mass spectrometry(SIMS), four-point probe and $\alpha-step.$ Annealing at 80$0^{\circ}C$ or higher resulted in conversion of the amorphous phase into predominantly MoS$i_2$and a lower sheet resistance. There was no significant out-diffusion of dopants from both single crystal and polycrystalline silicon substrate into molybdenum silicide layers during annealing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.151-151
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• 2009

Recently, there has been increasing interest in amorphous oxide semiconductors to find alternative materials for an amorphous silicon or organic semiconductor layer as a channel in thin film transistors(TFTs) for transparent electronic devices owing to their high mobility and low photo-sensitivity. The fabriction of amorphous oxide-based TFTs at room temperature on plastic substrates is a key technology to realize transparent flexible electronics. Amorphous oxides allows for controllable conductivity, which permits it to be used both as a transparent semiconductor or conductor, and so to be used both as active and source/drain layers in TFTs. One of the materials that is being responsible for this revolution in the electronics is indium-zinc-tin oxide(IZTO). Since this is relatively new material, it is important to study the properties of room-temperature deposited IZTO thin films and exploration in a possible integration of the material in flexible TFT devices. In this research, we deposited IZTO thin films on polyethylene naphthalate substrate at room temperature by using magnetron sputtering system and investigated their properties. Furthermore, we revealed the fabrication and characteristics of top-gate-type transparent TFTs with IZTO layers, seen in Fig. 1. The experimental results show that by varying the oxygen flow rate during deposition, it can be prepared the IZTO thin films of two-types; One a conductive film that exhibits a resistivity of $2\times10^{-4}$ ohm${\cdot}$cm; the other, semiconductor film with a resistivity of 9 ohm${\cdot}$cm. The TFT devices with IZTO layers are optically transparent in visible region and operate in enhancement mode. The threshold voltage, field effect mobility, on-off current ratio, and sub-threshold slope of the TFT are -0.5 V, $7.2\;cm^2/Vs$, $\sim10^7$ and 0.2 V/decade, respectively. These results will contribute to applications of select TFT to transparent flexible electronics.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.29 no.6
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• pp.383-388
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• 2019

High purity SiC fine powder with metal impurity contents of less than 1 ppm was synthesized by improved carbothermal reduction process, and the synthesized powder was used for SiC single crystal growth in RF heating PVT device at temperature above 2,100℃. In-situ x-ray image analyzer was used to observe the sublimation of the powder and single crystal growth behavior during the growth process. SiC powder was used as a source of single crystal growth, exhausted from the outside of the graphite crucible at the growth temperature and left graphite residues. During the growth, the flow of raw materials was concentrated in the middle and influenced the growth behavior of SiC single crystals. This is due to the difference in temperature distribution inside the crucible due to the fine powder. After the single crystal growth was completed, the single crystal ingot was cut into a 1 mm thick single crystal substrate and finely polished using a diamond abrasive slurry. A dark yellow 4H-SiC was observed overall of single crystal substrate, and the polycrystals generated in the outer part may be caused by the incorporation of impurities such as the bubble layer mixed in the process of attaching the seed crystal to the seed holder.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.478-478
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• 2012

Recently, there are many researches in order to increase the deposition rate (D/R) and improve film uniformity and quality in the deposition of microcrystalline silicon thin film. These two factors are the most important issues in the fabrication of the thin film solar cell, and for the purpose of that, several process conditions, including the large area electrode (more than 1.1 X 1.3 (m2)), higher pressure (1 ~ 10 (Torr)), and very high frequency regime (VHF, 40 ~ 100 (MHz)), have been needed. But, in the case of large-area capacitively coupled discharges (CCP) driven at frequencies higher than the usual RF (13.56 (MHz)) frequency, the standing wave and skin effects should be the critical problems for obtaining the good plasma uniformity, and the ion damage on the thin film layer due to the high voltage between the substrate and the bulk plasma might cause the defects which degrade the film quality. In this study, we will propose the new concept of the large-area multi-electrode (a new multi-electrode concept for the large-area plasma source), which consists of a series of electrodes and grounds arranged by turns. The experimental results with this new electrode showed the processing performances of high D/R (1 ~ 2 (nm/sec)), controllable crystallinity (~70% and controllable), and good uniformity (less than 10%) at the conditions of the relatively high frequency of 40 MHz in the large-area electrode of 280 X 540 mm2. And, we also observed the SEM images of the deposited thin film at the conditions of peeling, normal microcrystalline, and powder formation, and discussed the mechanisms of the crystal formation and voids generation in the film in order to try the enhancement of the film quality compared to the cases of normal VHF capacitive discharges. Also, we will discuss the relation between the processing parameters (including gap length between electrode and substrate, operating pressure) and the processing results (D/R and crystallinity) with the process condition map for ${\mu}c$-Si:H formation at a fixed input power and gas flow rate. Finally, we will discuss the potential of the multi-electrode of the 3.5G-class large-area plasma processing (650 X 550 (mm2) to the possibility of the expansion of the new electrode concept to 8G class large-area plasma processing and the additional issues in order to improve the process efficiency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.16 no.4
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• pp.36-46
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• 1979

Using N_ Ch silicon gate technology . the capacitors and transistors with various dimenssion were fabricated. Although the applied process was somewhat standard the conditions of ion implantation for the gate were varied by changing the implant energies from 30keV to 60keV for B and from 100 keV to 175keV for P . The doses of the implant also changed from 3 $\times$ 10 /$\textrm{cm}^2$ to 5 $\times$ 10 /$\textrm{cm}^2$ for B and from 4$\times$ 10 /$\textrm{cm}^2$ to 7 $\times$ 10 /$\textrm{cm}^2$ for P . The D. C. parameters such as threshold voltage. substrate doping level, the degree of inversion, capacitance. flat band voltage, depletion layer width, gate oxide thickless, surface states, motile charge density, electron mobility. leakage current were evaluated and also compared with the corresponing theoretical values and / or good numbers for application. The threshold voltages measured using curve tracer and C-V plot gave good agreements with the values calculated from SUPREM II which has been developed by Stanford University process group. The threshold vol tapes with back gate bias were used to calculate the change of the substrate doping level. The measured subthreshold slope enabled the prediction of the degree of inversion The D. C. testing results suggest the realized capacitors and transistors are suited for the memory applications.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.135-145
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• 2006

This paper presents the theory, design, fabrication and characterization of the novel low actuation voltage capacitive shunt RF-MEMS switch using a corrugated membrane with HRS MEMS packaging. Analytical analyses and experimental results have been carried out to derive algebraic expressions for the mechanical actuation mechanics of corrugated membrane for a low residual stress. It is shown that the residual stress of both types of corrugated and flat membranes can be modeled with the help of a mechanics theory. The residual stress in corrugated membranes is calculated using a geometrical model and is confirmed by finite element method(FEM) analysis and experimental results. The corrugated electrostatic actuated bridge is suspended over a concave structure of CPW, with sputtered nickel(Ni) as the structural material for the bridge and gold for CPW line, fabricated on high-resistivity silicon(HRS) substrate. The corrugated switch on concave structure requires lower actuation voltage than the flat switch on planar structure in various thickness bridges. The residual stress is very low by corrugating both ends of the bridge on concave structure. The residual stress of the bridge material and structure is critical to lower the actuation voltage. The Self-alignment HRS MEMS package of the RF-MEMS switch with a $15{\Omega}{\cdot}cm$ lightly-doped Si chip carrier also shows no parasitic leakage resonances and is verified as an effective packaging solution for the low cost and high performance coplanar MMICs.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1504-1507
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• 1999

We have grown vertically aligned carbon nanotubes in a large area of Co-Ni codeposited Si substrates by the thermal CVD using $C_2H_2$ gas. Since the discovery of carbon nanotubes, Synthesis of carbon nanotubes for mass production has been achieved by several methods such as laser vaporization arc discharge, and pyrolysis. In particular, growth of vertically aligned nanotubes is of technological importance for applications to FED. Recently, vertically aligned carbon nanotubes have been grown on glass by PECVD Aligned carbon nanotubes can be also grown on mesoporous silica and Fe patterned porous silicon using CVD. Despite such breakthroughs in the growth, the growth mechanism of the alignment are still far from being clearly understood. Furthermore, FED has not been clearly demonstrated yet at a practical level. Here, we demonstrate that carbon nanotubes can be vertically aligned on catalyzed Si substrate when the domain density reaches a certain value. We suggest that steric hindrance between nanotubes at an initial stage of the growth forces nanotubes to align vertically and then nanotubes are further grown by the cap growth mechanism.

• Journal of the Korean Magnetics Society
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• v.15 no.5
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• pp.287-291
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• 2005

We have investigated and tried to improve the characteristics of the thin $HfO_2$ layer deposited by ALD for fabricating a MOSFET device where the $HfO_2$ film worked as the gate dielectric. The substrate of MOSFET device is p-type (100) silicon wafer over which the $HfO_2$ dielectric layer with thickness of $5\~6\;nm$ has been deposited. Then the $HfO_2$ film was annealed with $1\~20\;atm\;H_2$ gas and subsequently aluminum electrodes was made so that the active area was $5{\times}10^{-5}\;cm^2$. We have found out that the drain current and transconductance increased by $5\~10\%$ when the $H_2$ gas pressure was 20 atm, which significantly contributed to the reliable operation of the high-density MOSFET devices.