• Journal of the Korean Ceramic Society
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• v.50 no.1
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• pp.43-49
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• 2013

${\beta}$-SiC was deposited onto a graphite substrate by a LPCVD method and the effect of the crystallographic orientation on mechanical properties of the deposited SiC was investigated. The deposition was performed at $1300^{\circ}C$ in a cylindrical hot-wall LPCVD system by varying the deposition pressure and total flow rate. The texture and crystallographic orientation of the SiC were evaluated by XRD. The deposition rate increased linearly with the gas flow rate from 800 sccm to 1600 sccm. It also increased with the pressure but became saturated above a total pressure of 3.3 kPa. In the range of 3.3 - 10 kPa, the preferred orientation changed from the (220) and (311) planes to the (111) plane. The hardness and elastic modulus showed maximum values when the SiC had the (111) preferred orientation, though it gradually decreased upon a change to the (220) and (311) preferred orientations.

• ETRI Journal
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• v.34 no.6
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• pp.950-953
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• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.77-86
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• 1998

A two-chip humidity sensor system has been developed which consists of a capacitive sense element die and a CMOS interface chip. The sense element was fabricated using thin polyimide films on (100) silicon substrate and showed excellent linearity(0.72%FS), low hysteresis (<3%) and low temperature coefficient(-0.0285 ~-0.0542pF/K) over a wide range of relative humidity and temperature. The capacitance-relative humidity characteristic exhibited a drift of 2~3% after 9 weeks of exposure to 4$0^{\circ}C$/90%RH. The signal-conditioning circuitry was fabricated using an 1.2- ${\mu}{\textrm}{m}$, one poly double metal CMOS process. The measured output voltage of the sensor system was directly proportional to relative humidity and showed good agreement with theory.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.355-358
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• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.509-512
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• 2004

This paper proposed a new solid State Relay(SSR) structure that can replace the conventional SSR as a power IC. The photodiode arrays, the main part of this structure, were designed and integrated in the same power It chip with the output parts, LDMOSFET and BJT, on a SOI substrate. The fabrication of this input part shared the same output LDMOSFET fabrication processs, except the additional deposition of Silicon nitride($Si_3N_4$) for the photo-detection part. According to LED illumination intensites and photo detecting areas, we could obtain voltage of 0.49V ${\~}$0.52V and current of 5.5uA ${\~}$ 108uA respectively from the fabricated unit photodiode. The maximum value of the voltage and the current we could obtain from the photodiode array were 3.58V and 24.4uA respectively, and the voltage was enough to operate the output LDMOSFET

• Journal of IKEEE
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• v.22 no.1
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• pp.213-215
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• 2018

In this study, we fabricate amorphous carbon thin films on silicon substrates by DC sputtering method and investigate the optical property and photothermal characteristics. A representative amorphous carbon thin film has a absorption value of 97% at a wavelength of 1000 nm and shows a temperature increase of $3^{\circ}C$ from $21.1^{\circ}C$ to $24.1^{\circ}C$ during white light irradiation. In addition, the amorphous carbon film has a heating rate four times higher than that of the substrate during light irradiation for 50 sec.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.12
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• pp.1245-1249
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• 2015

This study investigated the reflection spectra of wrinkled metal/polymer multilayers. A wavy surface was self-assembled by annealing an aluminum-coated poly(methyl metacrylate) layer on a silicon substrate. The total and diffuse reflectance characteristics of the sample with additional metal coatings(aluminum or silver) were evaluated in the visible wavelength(400~800 nm) using a spectrophotometer. The results showed that the wrinkled surface enhanced the diffuse reflectance up to 40~50% in the lower-wavelength range, demonstrating its potential for applications to optical thin-film devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.75-75
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• 2015

Strong interactions between electromagnetic radiation and electrons at metallic interfaces or in metallic nanostructures lead to resonant oscillations called surface plasmon resonance with fascinating properties: light confinement in subwavelength dimensions and enhancement of optical near fields, just to name a few [1,2]. By utilizing the properties enabled by geometry dependent localization of surface plasmons, metal photonics or plasmonics offers a promise of enabling novel photonic components and systems for integrated photonics or sensing applications [3-5]. The versatility of the nanoplasmonic platform is described in this talk on three folds: our findings on an enhanced ultracompact photodetector based on nanoridge plasmonics for photonic integrated circuit applications [3], a colorimetric sensing of miRNA based on a nanoplasmonic core-satellite assembly for label-free and on-chip sensing applications [4], and a controlled fabrication of plasmonic nanostructures on a flexible substrate based on a transfer printing process for ultra-sensitive and noise free flexible bio-sensing applications [5]. For integrated photonics, nanoplasmonics offers interesting opportunities providing the material and dimensional compatibility with ultra-small silicon electronics and the integrative functionality using hybrid photonic and electronic nanostructures. For sensing applications, remarkable changes in scattering colors stemming from a plasmonic coupling effect of gold nanoplasmonic particles have been utilized to demonstrate a detection of microRNAs at the femtomolar level with selectivity. As top-down or bottom-up fabrication of such nanoscale structures is limited to more conventional substrates, we have approached the controlled fabrication of highly ordered nanostructures using a transfer printing of pre-functionalized nanodisks on flexible substrates for more enabling applications of nanoplasmonics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.2
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• pp.1-6
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• 1983

The reduction of threshold voltage and punchthrough voltage of short channel MOS transistors has been measured experimentally with silicon gate NMOS transistors. The effects of the gate oxide thickness and substrate doping concentration on the threshold voltage and punch-through voltage have also been measured with sample devices with boron implantation and gate oxide thickness of 50 nm and 70 nm. Hot electron emission has been measured by floating gate method for the samples with 3 ${\mu}{\textrm}{m}$ channel length. It has been concluded from this measurement that hot electron emission is not significant for the channel length of 3${\mu}{\textrm}{m}$.