• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.8
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• pp.8-14
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• 1998

A new process is developed to improve the electrical characteristics of high .beta. and low saturation voltage power transistor for lamp solenoid driver application. To prevent punch-through breakdown, appropriate combination of base doping and base width is necessary in the range of operating voltage of the circuit. The optimum values of base doping and sheet resistance are $Q_{D}$= $1.5{\times}10^{14}$atoms/$\textrm{cm}^2$ and $R_{s}$= 350 $\Omega/\square$ base wodtj $W_{B}$= $2.5{\mu}m$respectively. Under this condition it is possible to control $\beta$ of the transistor to 1500, maintaining $VB_{CBO}$ =200V. To reduce scattered distribution of .beta. of the devices on the wafer, it is necessary to improve emittter predeposition process. As a result, scattered distribution of .beta. of the devices on the wafer was reduced to 1/6 by using the new process. To improve collector to emitter forward voltage drop, $V_{ECF}$ of damper diode, an additional silicon etching process is used, which resulted in improving the value of $V_{eCF}$ from 2.8 V to 1.8V. With the suggested process superior device performance and higher yield are achieved.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.69-69
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• 2003

최근 trench capacitor, isolation trench, micro-electromechanical system(MEMS), micro-opto-electromechanical system(MOEMS)등의 다양한 기술에 적용될 고종횡비(HAR) 실리콘 식각기술연구가 진행되어 지고 있다. 이는 기존의 습식식각시 발생하는 결정방향에 따른 식각률의 차이에 관한 문제와 standard reactive ion etching(RIE) 에서의 낮은 종횡비와 식각률에 기인한 문제점들을 개선하기 위해 고밀도 플라즈마를 이용한 건식식각 장비를 사용하여 고종횡비(depth/width), 높은 식각률을 가지는 이방성 트랜치 구조를 얻는 것이다. 초기에는 주로 HBr chemistry를 이용한 연구가 진행되었는데 이는 식각률이 낮고 많은양의 식각부산물이 챔버와 시편에 재증착되는 문제가 발생하였다. 또한 SF6 chemistry의 사용을 통해 식각률의 향상은 가져왔지만 화학적 식각에 기인한 local bowing과 같은 이방성 식각의 문제점들로 인해 최근까지 CHF3, C2F6, C4F8, CF4등의 첨가가스를 이용하여 측벽에 Polymer layer의 식각보호막을 형성시켜 이방성 구조를 얻는 multi_step 공정이 일반화 되었다. 이에 본 연구에서는 SF6 chemistry와 소량의 02/HBr의 첨가가스를 이용한 single_step 공정을 통해 공정의 간소화 및 식각 프로파일을 개선하여 최적의 HAR 실리콘 식각공정 조건을 확보하고자 하였다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2000.11a
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• pp.29-32
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• 2000

Cerium oxide thin film has been proposed as a buffer layer between the ferroelectric film and the Si substrate in Metal-Ferroelectric-Insulator-Silicon (MFIS ) structures for ferroelectric random access memory (FRAM) applications. In this study, CeO$_2$thin films were etched with Cl$_2$/Ar gas combination in an inductively coupled plasma (ICP). The highest etch rate of CeO$_2$film is 230 $\AA$/min at Cl$_2$/(Cl$_2$+Ar) gas mixing ratio of 0.2. This result confirms that CeO$_2$thin film is dominantly etched by Ar ions bombardment and is assisted by chemical reaction of Cl radicals. The selectivity of CeO$_2$to YMnO$_3$was 1.83. As a XPS analysis, the surface of etched CeO$_2$thin films was existed in Ce-Cl bond by chemical reaction between Ce and Cl. The results of XPS analysis were confirmed by SIMS analysis. The existence of Ce-Cl bonding was proven at 176.15 (a.m.u.).

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Journal of the Korean Ceramic Society
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• v.31 no.7
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• pp.753-758
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• 1994

(100) Si and 4$^{\circ}$off (100) Si were oxidized in dry oxygen, and the differences in thermal oxidation behavior and electrical characteristics between two specimens were investigated. Ellipsometer measurements of the oxide thickness produced by oxidation in dry oxygen from 1000 to 120$0^{\circ}C$ showed that the oxidation rates of the 5$^{\circ}$ off (100) Si were more rapid than those of the (100) Si and the differences between them decreased as the oxidation temperature increased. The activation energies based on the parabolic rate constant, B for (100) and 4$^{\circ}$off (100) Si were 25.8, 28.6 kcal/mol and those on the linear rate constant, B/A were 56.8, 54.9 kcal/mol, respectively. Variation of C-V characteristics with the oxidation temperature showed that the flat band voltages were shifted positively and surface state charge densities decreased as the oxidation temperature increased, and the surface state charge density of the 4$^{\circ}$off (100) Si was lower than that of the (100) Si. Also considerable decrease in the density of oxidation induced stacking faults (OSF) for the 4$^{\circ}$off (100) Si was observed through optical microscopy after preferentially etching off the oxide layer.

• Proceedings of the Korea Association of Crystal Growth Conference
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• 1999.06a
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• pp.115-127
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• 1999

The charged clusters or particles, which contain hundreds to thousands of atoms or even more, are suggested to form in the gas phase in the thin film processes such as CVD, thermal evaporation, laser ablation, and flame deposition. All of these processes are also used in the gas phase synthesis of the nanoparticles. Ion-induced or photo-induced nucleation is the main mechanism for the formation of these nanoclusters or nanoparticles inthe gas phase. Charged clusters can make a dense film because of its self-organizing characteristics while neutral ones make a porous skeletal structure because of its Brownian coagulation. The charged cluster model can successfully explain the unusual phenomenon of simultaneous deposition and etching taking place in diamond and silicon CVD processes. It also provides a new interpretation on the selective deposition on a conducting material in the CVDd process. The epitaxial sticking of the charged clusters on the growing surface is gettign difficult as the cluster size increases, resulting in the nanostructure such as cauliflowr or granular structures.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1893-1895
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• 2001

In this paper, novel release technique using wet etch is proposed. The results of this technique and the results of SAMs (Self-Assembled monolayers) coated after release using this technique are compared. Fabricated structure have 100 um in width and experimental length is from 100 um to 1 mm. Thickness of aluminum sacrificial layer is 2 um and structure thickness is 2.5 um. Cantilevers and bridges are fabricated with electroplated gold and silicon nitride deposited on substrate. An aluminium sacrificial layer was evaporated thermally and removed in various wet etching solutions. Detachment length of cantilever is 200 um and detachment length of bridge is 1 mm after isooctane rinsing. And the SAMs coating condition which is appropriate for gold and nitride are studied respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• Proceedings of the KSME Conference
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• 2003.04a
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• pp.980-986
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• 2003

As the ultra precision grinding can be applied to wafering process by the refinement of the abrasive, the development of high stiffness equipment and grinding skill, the conventional wafering process which consists of lapping, etching, Ist, 2nd and 3rd polishing could be exchanged to the new process which consists of precision surface grinding, final polishing and post cleaning. Especially, the ultra precision grinding of wafer improves the flatness of wafer and the efficiency of production. Futhermore, it has been not only used in bare wafer grinding, but also applied to wafer back grinding and SOI wafer grinding. This paper focused on the effect of the wheel path density and relative velocity on the characteristic of ground wafer in in-feed grinding with cup-wheel. It seems that the variation of the parameters in radial direction of wafer results in the non-uniform surface quality over the wafer. So, in this paper, the geometric analysis on grinding process is carried out, and then, the effect of the parameters on wafer surface quality is evaluated