• 전기전자학회논문지
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• 제13권4호
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• pp.23-27
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• 2009

실리콘 기판 상에 MBE (molecular beam epitaxy)로 형성된 GaSb 기반 p-channel HEMT 소자를 제작하기 위하여 오믹 접촉 형성 공정과 식각 공정을 연구하였다. 먼저 각 소자의 절연을 위한 메사 식각 공정 연구를 수행하였으며, HF기반의 습식 식각 공정과 ICP(inductively coupled plasma)를 이용한 건식 식각 공정이 모두 사용되었다. 이와 함께 소스/드레인 영역 형성을 위한 오믹 접촉 형성 공정에 관한 연구를 진행하였으며 Ge/Au/Ni/Au 금속층 및 $300^{\circ}C$ 60초 RTA공정을 통해 $0.683\;{\Omega}mm$의 접촉 저항을 얻을 수 있었다. 더불어 HEMT 소자의 게이트 형성을 위한 게이트 리세스 공정을 AZ300 현상액과 citric산 기반의 습식 식각을 이용하여 연구하였으며, citric산의 경우 소자 구조에서 캡으로 사용된 GaSb와 베리어로 사용된 AlGaSb사이에서 높은 식각 선택비를 보였다.

• 한국세라믹학회지
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• 제42권3호
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• pp.178-181
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• 2005

Silicon oxynitride (SiON) 막은 플라즈마 화학기상증착법(PECVD)으로 $SiH_4,\;N_2O$와 $N_2$ 가스를 사용하여 $SiO_2/Si$ 위해 증착되었다. 증착 변수에 따라서 SiON 막의 굴절률은 prism coupler를 사용하여 1552nm 파장에서 $1.4480\~1.4958$까지 변화하였다. 평판 광도파로 코어로 사용되는 SiON 막의 두께는 $6{\mu}m$이고, buffer 막과의 굴절률 차이(An)는 $0.36\%$이다. 또한 식각 공정으로 $SiO_2$ 막 위에 증착된 SiON 막은 건식식각을 통해서 수행되었다. 광화이버에 $1.55{\mu}m$ 파장의 레이저론 입력단에 조사하였다. 결과적으로 저굴절률 차이 SiON 광도파로를 제작하였으며, 출력단에서 single-mode 형상을 확인하였다.

• 센서학회지
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• 제30권5호
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• pp.273-278
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• 2021

Here, we studied the change in the mechanical stiffness of a diaphragm according to the corrugation pattern. The diaphragm consists of a silicon oxide and nitride double layer; a corrugation pattern was formed by dry etching, and the diaphragm was released by wet etching. The fabrication of the thin film was verified using focused ion beam and scanning electron microscopy images. The mechanical stiffness of the diaphragm was obtained by measuring the surface vibration using a laser Doppler vibrometer while applying external sound pressure. Flat squares, diaphragms with square corrugations, and circular corrugation patterns were measured and compared. The stiffness of the diaphragm with a corrugation structure was found to be smaller than that without a corrugation structure; in particular, circular corrugation showed a better effect because of the high symmetry. Furthermore, the effect of corrugation was theoretically predicted. The proposed corrugated diaphragm showed comparable flexibility with the state-of-the-art MEMS microphone diaphragm.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1998년도 추계학술대회
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• pp.147-148
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• 1998

In this paper, we developed the process for depth-probe type silicon microelectrode arrays. The process consists of four mask steps only. The steps are for defining sites, windows, and for shaping probe using plasma etch from above, and for shaping using wet etch from below, respectively. The probe thickness is controlled by dry etching, not by impurity diffusion. We used gold electrodes with a triple dielectric system consisting of oxide/nitride/oxide. The shank of the probe taper from 200um to tens of urn tip and has 30 um thickness.

• Bulletin of the Korean Chemical Society
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• 제33권1호
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• pp.83-89
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• 2012

Due to the potential importance and usefulness, usage of highly ordered nanoporous anodized aluminum oxide can be broadened in industry, when highly ordered anodized aluminum oxide can be placed on a substrate with controlled thickness. Here we report a facile route to highly ordered nanoporous alumina with the thickness of hundreds-of-nanometer on a silicon wafer substrate. Hexagonally or tetragonally ordered nanoporous alumina could be prepared by way of thermal imprinting, dry etching, and anodization. Adoption of reusable polymer soft molds enabled the control of the thickness of the highly ordered porous alumina. It also increased reproducibility of imprinting process and reduced the expense for mold production and pattern generation. As nanoporous alumina templates are mechanically and thermally stable, we expect that the simple and costeffective fabrication through our method would be highly applicable in electronics industry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.29-32
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• 2009

기공의 밀도가 높은 다공성 실리콘 산화물 박막이 GaAs 기판 상에 형성이 되었다. 다공성 실리콘 산화막을 형성하기 위해서 자기조립 형태로 배열하는 블록공중합체를 사용하였다. GaAs 기판 상에 화학기상증착 (CVD)을 이용하여 실리콘 산화막을 형성하였다. 폴리스티렌 (PS) 바탕에 벌집 형태로 배열된 폴리메틸메타아크릴레이트 (PMMA)가 주기적으로 배열되어 있는 나노패턴 박막을 형성하였고 PMMA를 아세트 산으로 제거하여 PS만 남아있는 나노크기의 마스크를 형성하였다. 형성된 PS 나노패턴의 지름은 15 nm, 박막의 두께는 40 nm 였으며 이를 건식 식각용 마스크로 사용하여 화학반응성식각 (RIE) 을 진행하였고 PS의 나노패턴이 산화막 기판상에 전사되도록 하였다. 식각 시간을 조절하여 산화막에 형성된 기공이 GaAs 표면까지 연결되도록 하였고 이는 불산으로 산화막을 제거하여 확인하였다. 식각시간은 90초에서 110초였으며 산화막 상에 나노패터닝된 기공이 형성되는 식각 시간은 90초에서 100초 사이였다. 형성된 나노 패터닝된 산화막 기공의 지름은 20~22 nm였고 식각 시간에 따라서 조절이 가능함을 확인할 수 있었다.

• 대한전자공학회논문지
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• 제27권10호
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• pp.106-112
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• 1990

다공질 실리콘을 열산화할 때 산화의 온도 의존성과 IR흡수 스펙트럼을 조사하여 다공질 실리콘외 산화특성을 조사하였다. PSL(porous silicon layer)을 $700^{\circ}C$에서 1시간, $1100^{\circ}C$에서 1시간으로 2단계 습식산화시켜 bulk 실리콘의 열산화막과 같은 성질의 수십 ${\mu}m$두께의 OPSL(oxidized porous silicon layer)을 짧은 시간에 형성시킬 수 있으며, 식각율과 항복전계는 산화온도와 산화 분위기에 크게 의존하는 것으로 나타났다. 이때 PSL의 산화율은 약 390nm/s이고, 항복전계는 1.0MV/cm~2.0MV/cm의 분포를 갖는다. 웨이퍼 휨을 측정하여 고온 열산화시 발생하는 산화막의 stress를 조사하였다. $1000^{\circ}C$ 이상의 고온에서 건식산화할 경우 발생하는 stress는 ${10^2}dyne/{cm^2}~{10^10}dyne/{cm^2}$로 측정되었다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2007년도 춘계학술발표회 초록집
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• pp.78-79
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• 2007

In this study, chemical dry characteristics of silicon nitride layers were investigated in the $F_2/N_2/Ar$ remote plasma. A toroidal-type remote plasma source was used for the generation of remote plasmas. The effects of additive $N_2$ gas on the etch rates of various silicon nitride layers deposited using different deposition techniques and precursors were investigated by varying the various process parameters, such as the $F_2$ flow rate, the addition $N_2$ flow rate and the substrate temperature. The etch rates of the various silicon nitride layers at the room temperature were initially increased and then decreased with the $N_2$ flow increased, which indicates an existence of the maximum etch rates. The etch rates of the silicon oxide layers were also significantly increased with the substrate temperature increased. In the present experiments the $F_2$ gas flow, addition $N_2$ flow rate and the substrate temperature were found to be the critical parameters in determining the etch rate of the silicon nitride layers

• ETRI Journal
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• 제38권4호
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• pp.685-694
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• 2016

A surface micromachined piezoresistive pressure sensor with a novel internal substrate vacuum cavity was developed. The proposed internal substrate vacuum cavity is formed by selectively etching the silicon substrate under the sensing diaphragm. For the proposed cavity, a new fabrication process including a cavity side-wall formation, dry isotropic cavity etching, and cavity vacuum sealing was developed that is fully CMOS-compatible, low in cost, and reliable. The sensitivity of the fabricated pressure sensors is 2.80 mV/V/bar and 3.46 mV/V/bar for a rectangular and circular diaphragm, respectively, and the linearity is 0.39% and 0.16% for these two diaphragms. The temperature coefficient of the resistances of the polysilicon piezoresistor is 0.003% to 0.005% per degree of Celsius according to the sensor design. The temperature coefficient of the offset voltage at 1 atm is 0.0019 mV and 0.0051 mV per degree of Celsius for a rectangular and circular diaphragm, respectively. The measurement results demonstrate the feasibility of the proposed pressure sensor as a highly sensitive circuit-integrated pressure sensor.