• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.78-83
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• 1999

The bonding interface is dependent on the properties of surfaces prior to SDB(silicon wafer direct bonding). In this paper, we prepared silicon surfaces in several chemical solutions, and annealed bonding wafers which were combined with thermally oxidized wafers and bare silicon wafers in the temperature range of $600{\times}1000^{\circ}C$. After bonding, the bonding interface is investigated by an infrared(IR) topography system which uses the penetrability of infrared through silicon wafer. Using this procedure, we observed intrinsic bubbles at elevated temperatures. So, we verified that these bubbles are related to cleaning and drying conditions, and the interface oxides on silicon wafer reduce the formation of intrinsic bubbles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.828-831
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• 2001

A simple and versatile method of manufacturing semiconductor devices with pn-junctions used the silicon direct bonding technology with simultaneous impurity diffusion is suggested . Formation of p- or n- type layers was tried during the bonding procedure by attaching two wafers in the aqueous solutions of Al(NO$_3$)$_3$, Ga(NO$_3$)$_3$, HBO$_3$, or H$_3$PO$_4$. An essential improvement of bonding interface structural quality was detected and a model for the explanation is suggested. Diode, Dynistor, and BGGTO structures were fabricated and examined. Their switching characteristics are presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• Proceedings of the KIEE Conference
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• 1997.07d
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• pp.1267-1269
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• 1997

본 논문에서는 SDB(Silicon Direct Bonding) 기술을 적용하여 빠른 스위칭 속도 및 낮은 도통 전압을 갖는 1200v 10A n-ch IGBT를 제작하였다. 기존의 epi wafer를 이용한 IGBT 제작시 스위칭 속도 개선을 위한 전자조사 방법을 사용하지 않고 buffer의 농도를 증가시켜 아노드 영역의 정공 주입 효율을 제어하여 90ns의 스위칭 속도를 가지며, 2.0V의 도통전압을 갖는 IGBT를 구현하였으며, SDB IGBT 제작시 bonding 계면의 문제 및 표면의 particle 및 결함이 소자의 전기적 특성에 미치는 영향을 고찰하였으며, 이를 실험 결과와 비교 평가하였다.

• Journal of the Korean Ceramic Society
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• v.36 no.8
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.7
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• pp.424-432
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• 2000

The plasma surface treatment, using hydrogen gas, of the silicon wafer was investigated as a pretreatment for the application to silicon-on-insulator (SOI) wafers using the silicon direct bonding technique. The chemical reactions of hydrogen plasma with surfaces were used for both the surface activation and the removal of surface contaminants. As a result of exposure of silicon wafer to the plasma, an active oxide layer was formed on the surface, which was rendered hydrophilic. The surface roughness and morphology were estimated as functions of plasma exposing time as well as of power. The surface became smoother with decreased incident hydrogen ion flux by reducing plasma exposing time and power. This process was very effective to reduce the carbon contaminants on the silicon surface, which was responsible for a high initial surface energy. The initial surface energy measured by the crack propagation method was 506 mJ/m2, which was up to about three times higher than that of a conventional RCA cleaning method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.874-877
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• 2001

SOI(Silicon-On-Insulator) technology is proposed as an alternative to bulk silicon for MEMS(Micro Electro Mechanical System) manufacturing. In this paper, we fabricated the SOI wafer with uniform active layer thickness by silicon direct bonding and mechanical polishing processes. Specially-designed electrostatic bonding system is introduced which is available for vacuum packaging and silicon-glass wafer bonding for SOG(Silicon On Glass) wafer. We demonstrated thermopile sensor and RF resonator using the SOI wafer, which has the merits of simple process and uniform membrane fabrication.

• Journal of the Korean Ceramic Society
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• v.35 no.6
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.