• Current Photovoltaic Research
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• 제6권3호
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• pp.86-90
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• 2018

To generate more current in crystalline silicon solar cells, surface texturing is adopted by reducing the surface reflection. Conventionally, random pyramid texturing by the wet chemical process is used for surface texturing in crystalline silicon solar cell. To achieve higher efficiency of solar cells, well ordered inverted pyramid texturing was introduced. Although its complicated process, superior properties such as lower reflectance and recombination velocity can be achieved by optimizing the process. In this study, we investigated optical and passivation properties of inverted pyramid texture. Lifetime, implied-Voc and reflectance were measured with different width and size of the texture. Also, effects of chemical rounding at the valley of the pyramid were observed.

• 센서학회지
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• 제14권5호
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• pp.357-361
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• 2005

Low-stress silicon nitride (LSN) thin films with embedded metal line have been developed as free standing structures to keep microspheres in proper locations and localized heat source for application to a chip-based sensor array for the simultaneous and near-real-time detection of multiple analytes in solution. The LSN film has been utilized as a structural material as well as a hard mask layer for wet anisotropic etching of silicon. The LSN was deposited by LPCVD (Low Pressure Chemical Vapor Deposition) process by varing the ratio of source gas flows. The residual stress of the LSN film was measured by laser curvature method. The residual stress of the LSN film is 6 times lower than that of the stoichiometric silicon nitride film. The test results showed that not only the LSN film but also the stack of LSN layers with embedded metal line could stand without notable deflection.

• 센서학회지
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• 제20권3호
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• pp.207-212
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• 2011

In this study, pyramid structured black silicon process was developed in order to overcome disadvantages of using wet etching to texture the surface of single crystalline silicon and using grass/needle-like black silicon structure. In order to form the pyramidal black silicon structure on the silicon surface, the RIE system was modified to equip with metal-mesh on the top of head shower. The process conditions were : $SF_6/O_2$ gas flow 15/15 sccm, RF power of 200 W, pressure at 50 mTorr ~ 200 mTorr, and temperature at $5^{\circ}C$. The pressure did not affect the pyramid structure significantly. Increasing processing time increased the size of the pyramid, however, the size remained constant at 1 ${\mu}M$ ~ 2 ${\mu}M$ between 15 minutes ~ 20 minutes of processing. Pyramid structure of 1 ${\mu}M$ in size showed to have the lowest reflectivity of 7 % ~ 10 %. Also, the pyramid structure black silicon is more appropriate than the grass/needle-like black silicon when creating solar cells.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2008년도 추계학술대회 초록집
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• pp.90-90
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• 2008

실리콘을 기판으로 하는 대부분의 태양전지에서는 표면반사에 의한 광에너지손실을 최소화시키고자 습식에칭(wet etching)에 의한 텍스쳐링처리가 이루어진다. 그러나 습식 에칭은 공정 과정이 번거롭고 비용이 많이 든다. Inductively Coupled Plasma Etcher 장비를 이용한 플라즈마 에칭 (plasma etching)을 실리콘 표면에 적용하여 공정을 간단하고 저렴하게 하며 반사도를 획기적으로 낮추는 기술이 개발되었다. 습식 에칭으로 형성된 표면의 피라미드 구조는 1차 반사 후 빛의 일부가 외부로 흩어져 나가지만 플라즈마 에칭으로 형성된 나노구조는 내부전반사가 가능하여 대부분의 태양 에너지를 흡수한다. 나노구조는 필라(pillar)의 형태로 형성되며 이 필라의 길이에 따라 반사도가 다르게 나타난다. 이는 플라즈마 에칭 시 발생하는 이온폭격과 에칭 측벽 식각 보호막(SiOxFy : Silicon- Oxy- Fluoride)이 필라의 길이에 영향을 주기 때문이며, 필라가 길수록 반사도를 저하시킨다. 최저의 반사도를 얻기 위해서 나노필라 형성에 기여하는 플라즈마 에칭 시간, RF bias power, SF6/O2 gas ratio의 변화에 따른 실험이 진행되었다. 플라즈마 발생 초기에는 표면의 거칠기만 증가할 뿐 필라가 형성되지 않지만 특정조건에서 3um 이상의 필라를 얻는다. 이는 에칭 측벽 식각 억제막이 약한 부분으로 이온폭격이 집중되어 발생한다. 플라즈마 에칭을 적용하여 형성된 나노필라는 반사도가 가시광 영역에서 대략 1%에 불과하며, 마스크 없이 공정이 가능한 장점이 있다.

• 전자공학회논문지A
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• 제33A권7호
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• pp.149-155
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• 1996

A new technique wasdeveloped which obtains selectively the htick fully recessed oxidized porous silicon layer (OPSL) with good dielectric property. The porous silicon layer was ocnverted to thick fully recessed oxide (FRO) with 3-step (1${\mu}$m, 1.5${\mu}$m, 1.8${\mu}$m) by multi-step thermal oxidation (after 400$^{\circ}$C, 1 hour by dry oxidation, 700$^{\circ}$C, 1 hour and then 1100$^{\circ}$C, 1 hour by wet oxidation). The breakdwon field of the FRO was about 2.5MV/cm and the leakage current was several pA ~ 100 pA in the range of 0 of 90 pF. The progress of oxidation of a porous silicon layer was studied by examining the infrared abosrption spectra. The refractive index (1.51) of the fRO, which was measured by ellipsometer, was comparable to that of the thermally grown silicon dioxide (1.46). The etching rate (1600${\AA}$/min) of the FRO was also almost equal to that of the thermal oxide.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.361-364
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• 2008

Tips of probe card were fabricated using MEMS technology. P-type silicon wafer with $SiO_2$ layer was used as a substrate for fabricating the probe card. Ni-Cr and Au used as seed layer for electroplating Ni were deposited on the silicon wafer. Line patterns for probing devices were formed on silicon wafer by electroplating Ni through mold which formed by MEMS technology. Bridge structure was formed by wet-etching the silicon substrate. AZ-1512 photoresist was used for protection layer of back side and DNB-H100PL-40 photoresist was used for patterning of the front side. The mold with the thickness of $60{\mu}m$ was also formed using THB-120N photoresist and probe tip with thickness of $50{\mu}m$ was fabricated by electroplating process.

• 한국연소학회:학술대회논문집
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• 한국연소학회 2006년도 제33회 KOSCO SYMPOSIUM 논문집
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• pp.235-241
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• 2006

Catalytic combustion is one of the suitable methods for micro power source due to high energy density and no flame quenching. Catalyst loading in the micro structured combustion chamber is one of the most important issues in the development of micro catalytic combustors. In this research, to coat catalyst on the chamber wall, two methods were investigated. First, $Al_2O_3$ was selected as a support of Pt and $Pt/Al_2O_3$ was synthesized through the alumina sol-gel procedure. To improve the coating thickness and adhesion between catalyst and substrate, heat resistant and water solvable organic-inorganic hybrid binder was used. Porous silicon was also investigated as a catalyst support for platinum. Through the parametric studies of current density and etching time, fabrication process of $1{\sim}2{\mu}m$ of diameter and about $25{\mu}m$ depth pores was confirmed. Coated substrates were test in the micro channel combustor which was fabricated by the wet etching and machining of SUS 304. Using $Pt/Al_2O_3$ coated substrate and Pt coated porous silicon substrate, conversion rate of fuel was over 95% for $H_2$/Air premixed gas.

• 한국연소학회지
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• 제11권2호
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• pp.7-14
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• 2006

Catalytic combustion is one of the suitable methods for micro power source due to high energy density and it can be applied to micro structured chamber without consideration of quenching since it is flameless combustion. Catalyst loading in the micro structured combustion chamber is one of the most important issues in the development of micro catalytic combustors. In this research, to coat catalyst on the chamber wall, two methods were investigated. First, $Al_2O_3$ was selected as a support of Pt and $Pt/Al_2O_3$ was synthesized through the alumina sol-gel procedure. To improve the coating thickness and adhesion between catalyst and substrate, heat resistant and water solvable organic-inorganic hybrid binder was used. Porous silicon was also investigated as a catalyst support for platinum. Through the parametric studies of current density and etching time, fabrication process of $1{\sim}2{\mu}m$ of diameter and about $25{\mu}m$ depth pores was confirmed. Coated substrates were test in the micro channel combustor which was fabricated by the wet etching and machining of SUS 304. Using $Pt/Al_2O_3$ coated substrate and Pt coated porous silicon substrate, conversion rate of fuel was over 95 % for $H_2/Air$ premixed gas.

• 센서학회지
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• 제15권1호
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• pp.1-6
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• 2006

We fabricated Si nano-wire MOSFET by using the conventional photolithography with a $1.5{\mu}m$ resolution. Si nano-wire was fabricated by using reactive ion etching (RIE), anisotropic wet etching and thermal oxidation on a silicon-on-insulator (SOI) substrate, and its width is 30 nm. Logarithmic circuit consisting of a NMOSFET and Si nano-wire MOSFET has been constructed for application to high-sensitivity image sensor. Its sensitivity was 1.12 mV/lux. The output voltage swing was 1.386 V.

• 마이크로전자및패키징학회지
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• 제15권2호
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• pp.63-67
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• 2008

전자산업의 소형화와 경량화 추세에 맞추어 최근 집적 칩(IC)이나 패키지를 적층시키는 삼차원 집적화(3D integration) 기술 개발은 차세대 핵심기술로 중요시되고 있다. 본 연구에서는 삼차원 집적화 공정 기술 중 하나인 초박막 실리콘 웨이퍼 연삭(grinding)공정이 웨이퍼 표면에 미치는 영향에 대해서 조사하였다. 실리콘 웨이퍼를 약 $30{\mu}m$과 $50{\mu}m$ 두께까지 연삭한 후, 미세연삭(fine grinding) 단계까지 처리된 시편을 건식 연마(dry polishing) 또는 습식 애칭(wet etching)으로 표면 처리된 시편들과 비교 분석하였다. 박막 웨이퍼 두께는 전계방시형 주사전자현미경과 적외선 분광기로 측정하였고, 표면 특성 분석을 위해선 표면주도(roughness), 표면손상(damage), 경도를 원자현미경, 투과정자현미경 그리고 나노인덴터(nano-indentor)를 이용하여 측정하였다. 표면 처리된 시편의 특성이 표면 처리되지 않은 시편보다 표면주도와 표면손상 등에서 현저히 우수함을 확인 할 수 있었으나, 경도의 경우 표면 처리의 유무에 관계없이 기존의 벌크(bulk)실리콘 웨이퍼와 오차범위 내에서 동일한 것으로 보였다.