• 한국결정성장학회지
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• 제20권1호
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• pp.7-11
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• 2010

단결정 실리콘 태양전지의 광학적 손실을 감소시키는 표면 텍스쳐링은 최종 셀의 효율을 향상시키기 위하여 매우 중요하다. 본 연구에서는 2-step texturing의 공정으로 기존의 텍스쳐링에서 이루어진 피라미드에 수 많은 sub-micrometer 사이즈의 구조를 형성시켰다. $AgNO_3$ 용액으로 웨이퍼 표면에 Ag코팅을 한 후, 그 웨이퍼를 다시 HF/$H_2O_2$ 용액으로 수십초 동안 식각을 거치게 된다. 결과적으로, 피라미드 위에 생성된 수 nm사이즈의 구조물들은 $AgNO_3$의 농도 및 식각 시간의 변화에 의해 그 크기와 굵기가 변화하는 것을 알 수 있었다. 웨이퍼의 표면이 2-step texturing에 의해 식각이 이루어지면 연잎의 거친 표면과 비슷해지고, 그 결과 평균 10% 이상의 반사율을 보이던 기존 웨이퍼에서 3% 이하의 낮은 반사율을 얻을 수 있었다. 이는 일반적인 텍스쳐링과 anti-reflection coating을 거친 웨이퍼의 반사율보다 낮은 결과이다.

• 센서학회지
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• 제5권3호
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• pp.101-108
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• 1996

Au 또는 Pt를 확산시켜 실리콘 $p^{+}-n$ 접합 다이오드를 제작하였다. Au 또는 Pt의 확산을 $800{\sim}1010^{\circ}C$, 산소 및 질소분위기에서 실시하여 다이오드의 전기적 특성을 분석하였으며, Au 또는 Pt가 확산된 시편을 산소분위기의 $800{\sim}1010^{\circ}C$에서 2차 열처리를 실시한후 이 처리가 소자의 전기적 특성에 미치는 효과에 대해 고찰하였다. $1010^{\circ}C$의 온도에서 1차 확산결과 Pt가 확산된 다이오드의 누설전류는 Au가 확산된 다이오드 누설전류의 75배 였다. $1010^{\circ}C$, 질소분위기에서 1시간동안 Pt가 확산된 시편을 산소분위기에서 $800^{\circ}C$, 1시간동안 2차 열처리하였을 경우에 1차 열처리한 것보다 누설전류가 1/1100로 감소되었다. 초고속 실리콘 $p^{+}-n$ 접합 스위칭 다이오드의 특성을 만족하기 위해서는, Pt를 $1010^{\circ}C$, 질소분위기에선 1시간 확산시킨후 2차 열처리를 $800^{\circ}C$, 산소분위기에서 1시간동안 열처리하는 것이 최적 조건임을 알 수 있었다. 이때 다이오드의 제특성은 역회복시간 4ns, 항복전압 138V, 누설전류1.7nA 그리고 순방향 전압이 1V였다.

• 한국재료학회지
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• 제8권6호
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• pp.532-537
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• 1998

본 연구는 반도체 공정중 습식세정시 사용되는 초순수내에서의 오존의 거동과 오존이 주입된 초순수와 실리콘 웨이퍼와의 반응성에 대해 연구하였다. 초순수내 오존의 용해도는 주입되는 오존의 농도와 초순수의 온도가 낮을수록 증가하였고 주입되는 오존의 농도에 정비례하여 증가하였다. 초순수내 오존의 반감기는 초순수내 오존의 용해농도와 초순수의온도가 낮을수록 증가함을 나타내었고 반응차수는 약 1.5로 계산되었다. 초순수의산화환원전위(redox potential)값은 오존 주입시 5분 이내에 포화되어 일정한 값을 나타내었고 주입되는 오존의 농도가 증가함에 따라 약간 증가하였다. HF처리된 실리콘 웨이퍼는 오존이 2ppm 이상 용해된 초순수에서 세정하였을 때 1분 이내에 접촉각이 $10^{\circ}$미만의 친수성 표면을 형성하였고 piranha 세정액($H_2SO_4$과 $H_2O_2$의 혼합액)에 의해 형성된 자연산화막보다 오존이 주입된 초순수에 의해 형성된 산화막이 약간 더 두꺼움을 Spectroscopic Ellip-someter에 의해 관찰하였다. 오존의 농도가 1.5ppm에서 90초내에 계면활성제로 오염된 실리콘 웨이퍼를 piranha용액과 오존이 함유된 황산 그리고 오존이 함유된 초순수에서 세정시 오존이 함유된 초순수가 가장 탁월한 오염제거능력을 나타내었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.411-411
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• 2012

Over the recent years, surface enhanced Raman spectroscopy (SERS) has dramatically grown as a label-free detecting technique with the high level of selectivity and sensitivity. Conventional SERS-active nanostructured layers have been deposited or patterned on rigid substrates such as silicon wafers and glass slides. Such devices fabricated on a flexible platform may offer additional functionalities and potential applications. For example, flexible SERS-active substrates can be integrated into microfluidic diagnostic devices with round-shaped micro-channel, which has large surface area compared to the area of flat SERS-active substrates so that we may anticipate high sensitivity in a conformable device form. We demonstrate fabrication of flexible SERS-active nanostructured substrates based on soft-lithography for simple, low-cost processing. The SERS-active nanostructured substrates are fabricated using conventional Si fabrication process and inkjet printing methods. A Si mold is patterned by photolithography with an average height of 700 nm and an average pitch of 200 nm. Polydimethylsiloxane (PDMS), a mixture of Sylgard 184 elastomer and curing agnet (wt/wt = 10:1), is poured onto the mold that is coated with trichlorosilane for separating the PDMS easily from the mold. Then, the nano-pattern is transferred to the thin PDMS substrates. The soft lithographic methods enable the SERS-active nanostructured substrates to be repeatedly replicated. Silver layer is physically deposited on the PDMS. Then, gold nanoparticle (AuNP) inks are applied on the nanostructured PDMS using inkjet printer (Dimatix DMP 2831) to deposit AuNPs on the substrates. The characteristics of SERS-active substrates are measured; topology is provided by atomic force microscope (AFM, Park Systems XE-100) and Raman spectra are collected by Raman spectroscopy (Horiba LabRAM ARAMIS Spectrometer). We anticipate that the results may open up various possibilities of applying flexible platform to highly sensitive Raman detection.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• Applied Microscopy
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• 제25권2호
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• pp.73-79
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• 1995

The oxidation of silicon wafers is an essential step in the fabrication of semiconductor devices. It is known to induce degradation of electrical properties and lattice strain of Si substrate from thermal oxidation process due to charged interface and thermal expansion mismatch from thermally grown SiO, film. In this study, convergent beam electron diffraction technique is employed to directly measure the lattice strains in Si(100) and $4^{\circ}$ - off Si(100) substrates with thermally grown oxide layer at $1200^{\circ}C$ for three hours. The ratios of {773}-{973}/{773}-{953} Higher Order Laue Zone lines were used at [012] zone axis orientation. Lattice parameters of the Si substrate as a function of distance from the interface were determined from the computer simulation of diffraction patterns. Correction value for the accelerating voltage was 0.2kV for the kinematic simulation of the [012]. HOLZ patterns. The change in the lattice strain profile before and after removal of oxide films revealed the magnitudes of intrinsic strain and thermal strain components. It was shown that $4^{\circ}$ -off Si(100) had much lower intrinsic strain as surface steps provide effective sinks for the free Si atoms produced during thermal oxidation. Thermal strain in the Si substrate was in compression very close to the interface and high concentration of Si interstitials appeared to modify the thermal expansion coefficient of Si.

• 대한기계학회논문집B
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• 제38권8호
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• pp.671-676
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• 2014

볼텍스 컵은 실린콘 웨이프 제조공정과 같이 민갑한 물체을 이송시키는 방법으로 제안되었다. 볼테스 컵의 상부에 위치한 노즐을 통해 공기를 공급하면 내부 실린더에서 큰 선회유동이 생성된다. 공기는 볼텍스 컵과 바닥면 사이의 틈새로 빠져나가면서 흡입압력을 생성시키고 물체를 들어 올릴 수 있게 된다. 본 논문에서는 볼텍스 컵에 관한 3차원 유동 해석을 통해 실험 결과와 해석 결과를 비교하여 해석의 신뢰성을 확인하였다. 그리고 볼텍스 컵의 길이 변화와 형상 변화를 주어 해석을 통해 흡입 압력 생성에 영향을 미치는 정도를 분석하였고, 볼텍스 컵 형상의 최적 조건을 제시하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 춘계학술대회 논문집
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• pp.1507-1510
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• 2005

This study was carried out as a part of the research on the development of a maskless and electroless process for fabricating metal micro/nanostructures by using a nanoindenter and an electroless deposition technique. $2-\mu{m}-deep$ indentation tests on Ni and Cu samples were performed. The elastic recovery of the Ni and Cu was 9.30% and 9.53% of the maximum penetration depth, respectively. The hardness and the elastic modulus were 1.56 GPa and 120 GPa for Ni and 1.49 GPa and 100 GPa for Cu. The effect of single-point diamond machining conditions such as the Berkovich tip orientation (0, 45, and $90^{\circ}$) and the normal load (0.1, 0.3, 0.5, 1, 3, and 5 mN), on both the deformation behavior and the morphology of cutting traces (such as width and depth) was investigated by constant-load scratch tests. The tip orientation had a significant influence on the coefficient of friction, which varied from 0.52-0.66 for Ni and from 0.46-0.61 for Cu. The crisscross-pattern sample showed that the tip orientation strongly affects the surface quality of the machined area during scratching. A selective deposition of Cu at the pit-like defect on a p-type Si(111) surface was also investigated. Preferential deposition of the Cu occurred at the surface defect sites of silicon wafers, indicating that those defect sites act as active sites for the deposition reaction. The shape of the Cu-deposited area was almost the same as that of the residual stress field.

• 한국결정성장학회지
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• 제4권4호
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• pp.347-355
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• 1994

솔-젤공정에 의하여 실리콘 웨이퍼 위에 형성한 $PbTiO_3$ 박막의 결정 구조 및 성분 분포에 미치는 열처리 효과를 고찰하기 위하여 $400^{\circ}C에서 750^{\circ}C$ 까지의 온도 범위에서 열처리를 수행하여 $440^{\circ}C$에서 열처리한 박막에서도 peroxskite 구조만을 갖는 박막이 형성됨을 새로이 발견하였다. $480^{\circ}C$에서 $550^{\circ}C$까지 열처리한 박막은 소량의 pyrochlore 구조가 함께 형성되 었으며 $600^{\circ}C$ 이상에서 열처리한 박막은 단지perovskite 구조만을 가졌으나 납의 승화가 급격 하게 증가하는 것이 관찰되었다.

• 한국정밀공학회지
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• 제29권5호
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• pp.563-571
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• 2012

In 3D integration package using TSV technology, bonding is the core technology for stacking and interconnecting the chips or wafers. During bonding process, however, warpage and high stress are introduced, and will lead to the misalignment problem between two chips being bonded and failure of the chips. In this paper, a finite element approach is used to predict the warpages and stresses during the bonding process. In particular, in-plane deformation which directly affects the bonding misalignment is closely analyzed. Three types of bonding technology, which are Sn-Ag solder bonding, Cu-Cu direct bonding and SiO2 direct bonding, are compared. Numerical analysis indicates that warpage and stress are accumulated and become larger for each bonding step. In-plane deformation is much larger than out-of-plane deformation during bonding process. Cu-Cu bonding shows the largest warpage, while SiO2 direct bonding shows the smallest warpage. For stress, Sn-Ag solder bonding shows the largest stress, while Cu-Cu bonding shows the smallest. The stress is mainly concentrated at the interface between the via hole and silicon chip or via hole and bonding area. Misalignment induced during Cu-Cu and Sn-Ag solder bonding is equal to or larger than the size of via diameter, therefore should be reduced by lowering bonding temperature and proper selection of package materials.