• 한국통신학회논문지
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• 제21권5호
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• 한국통신학회논문지
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• 제25권12B호
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• pp.2052-2059
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• 2000

Digital IF(Intermediate Frequency) 처리단과 같은 고속과 저전력을 요구하는 필터에서 덧셈기만을 사용하여 CSD(Canonical Signed Digit)형의 필터계수들을 구현하는 구조가 널리 연구되고 있다. 본 논문에서는 선형위상 FIR(Finite Impulse Response) 필터의 CSD형 필터계수들을 최소의 덧셈으로 구현할 수 있는 아키텍처를 제안한다. 1과 -1로 이루어진 필터계수 표에서 공통패턴을 공유함으로서 덧셈의 수를 줄이는 방법이 이미 연구되었다. 본 논문은 비트 shift, 비트 add, 비트 반전을 통하여 인공의 공통패턴을 만들어서 이미 존재하는 공통패턴에 합류시킴으로서 덧셈의 수를 더욱 줄일 수 있는 방법을 제안한다. CDMA 이동통신 단말기의 IF단에 사용되는 사양의 디지털 필터를 73탭의 CSD형 계수로 구현하여 9.2%의 덧셈 감소의 효과가 있음을 보였다.

• 전자공학회논문지C
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• 제34C권11호
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• pp.20-28
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• 1997

In this paper, quantization and inverse quantizatio unit, a sa component of MPEG-2 moving picture compression system, ar edesigned. In the processing of quantization, this design adopted newly designed arithmetic units in which quantization matrices and scale code was expressed with SD(signed-digit) code. In the arithmetic unit of inverse quantization, quantization scale code, which has 5-bits length, is splited into two pieces; 2-bits for control code, 3-bits for quantization data, and the method to devise quantization step size is proposed. The design was coded with VHDL and synthesis results in that it consumed about 6,110 gates, and operating speed is 52MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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• pp.183-186
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• 2002

In this paper, we present an area-efficient programmable FIR digital filter using canonic signed-digit(CSD) coefficients, in which the number of effective nonzero bits of each filter coefficient is reduced by sharing the shift and add logics for common nonzero bits between adjacent coefficients. Also, unused shift and add logics for a low- magnitude coefficient are reassigned to an appropriate high - amplitude coefficient. In consequence, the proposed architecture reduces the hardware area of a programmable FIR filter by about 24% and improves performance about 6-7dB compared to other multiplierless FIR filters with powers-of-two coefficients.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.511-512
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• 2006

Three stage(CIC-FIR-FIR) decimation filter in delta-sigma A/D converter for audio is designed. A canonical signed digit(CSD) code method is used to minimize area of multipliers. This filter is designed in 0.25um CMOS process and incorporates $1.36\;mm^2$ of active area. Measured results show that this decimation filter is suitable for digital audio A/D converters.

• 전기학회논문지
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• 제59권2호
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• pp.452-456
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• 2010

Multiplication is a fundamental arithmetic operation in many digital signal processing (DSP) and communication algorithms. The group CSD (GCSD) multiplier was recently proposed based on the variation of canonical signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In this paper, it is shown that, by exploiting the characteristics of the filter coefficients, GCSD multipliers can be used for the efficient implementation of time-multiplexed FIR filters.

• 전자공학회논문지A
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• 제31A권8호
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• pp.26-33
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• 1994

Optical adders using a modified signed-digit(MSD) number system have been proposed to restrict the carry propagation chain encountered in a conventional binary adder to two positions to the left. But, MSD number system must encode three different states to represent the three possible digits of MSD. In this paper, we propose the design of an optical adder based on 1-bit addition rules by using the method of symbolic substitution (SS). We show that this adder can use binary input which is used by a digital computer, as it is and be implemented by smaller system in size than MSD adder.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2004년도 추계학술대회
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• pp.131-133
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• 2004

이 논문에서는 MPEG audio 알고리즘의 필터뱅크를 덧셈을 사용하여 저전력으로 구현할 수 있는 구조를 제안하였다. 제안된 구조는 CSD(Canonic Signed Digit) 형의 계수를 사용하며, 입력신호 샘플을 최대로 공유함으로서 사용되는 덧셈기의 수를 최소화하였다. 제안된 구조는 알고리즘에서 사용된 공통입력 공유, 선형위상 대칭 필터계수를 이용한 공유, 공통입력을 이용한 블록 공유, CSD 형의 계수와 공통패턴 공유를 통하여 사용되는 덧셈의 수를 최소화할 수 있음을 보였다. Verilog-HDL 코딩을 통하여 시뮬레이션을 수행한 결과, 제안된 구조는 기존의 곱셈기 구조의 구현면적과 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 또한 제안된 구조의 전력소모도 곱셈기 구조와 비교하여 $59.6\%$를 감소시킬 수 있음을 보였다. 따라서 곱셈기가 내장된 DSP 프로세서를 사용하지 않고도, Arithmetic Unit나 마이크로프로세서를 사용하여 효과적으로 MPEG audio 필터뱅크를 구현할 수 있음을 보였다.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권2호
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• pp.111-117
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• 2004

The low-power design of the A/D converter is indispensable to achieve the compact bio-signal measuring device with long battery duration. In this paper, new decimation filter structure is proposed for the low-power design of the Sigma-Delta A/D converter in the bio-instruments. The proposed filter is based on the non-recursive structure of the CIC (Cascaded Integrator Comb) decimation filter in the Sigma-Delta A/D converter. By combining the CSD (Canonic Signed Digit) structure with common sub-expression sharing technique, the proposed decimation filter structure can significantly reduce the number of adders for implementation. For the fixed decimation factor of 16, the 15％ of power consumption saving is achieved in the proposed structure in comparison with that of the conventional polyphase CIC filter.

• 한국정보전자통신기술학회논문지
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• 제11권5호
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.