• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.632-639
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• 2002

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1867-1875
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• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1739-1747
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• 2004

In this paper, an efficient radix-4 systolic VLSI architecture for RSA public-key cryptosystem is proposed. Due to the simple operation of iterations and the efficient systolic mapping, the proposed architecture computes an n-bit modular exponentiation in n$^{2}$ clock cycles since two modular multiplications for M$_{i}$ and P$_{i}$ in each exponentiation process are interleaved, so that the hardware is fully utilized. We encode the exponent using Radix-4. SD (Signed Digit) number system to reduce the number of modular multiplications for RSA cryptography. Therefore about 20% of NZ (non-zero) digits in the exponent are reduced. Compared to conventional approaches, the proposed architecture shows shorter period to complete the RSA while requiring relatively less hardware resources. The proposed RSA architecture based on the modified Montgomery algorithm has locality, regularity, and scalability suitable for VLSI implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1451-1459
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• 2004

In this paper, a low-power 32-point IMDCT structure is proposed for MP3. Through re-odering of IMDCT matrices, we propose the systolic structure operating with 16, 8, 4, 2, and 1 cycle, respectively. To reduce power consumption, multiplication of each sub blocks are implemented by add and shift operation with CSD(Canrmic sigled digit) form coefficients. To reduce, furthermore, the number of adders, we utilize the common sub-expression sharing techniques. With these techniques, the relative power consumption of the proposed structure is reduced by 58.4% comparison to the conventional structure using only 2's complement form coefficient. Validity of the proposed structure is proved through Verilog-HDL coding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.662-665
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• 2002

This paper describes a novel converter to implement high-speed binary-to-residue conversion for moduli 2$^{n}$ - 1, 2$^{n}$ , 2$^{n}$ +2$^{\alpha}$/($\alpha$$\in$｛0,1,…,n-1｝) without using look-up table. In our implementation, the high-speed converter can be achieved, because of the modulo addition time is independent of the word length of operands by using the Signed-Digit (SD) adders inside the modulo adders. For a LSI implementation of residue SD number system with ordinary binary system, the proposed binary-to-residue converter is the efficient circuit.cient circuit.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.931-934
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• 2001

고정 계수를 갖는 곱셈기의 구현 시 면적과 전력소모를 줄이기 위해서 곱셈계수를 CSD(Canonic Signed Digit) 형태로 표현 할 수 있다. CSD 계수의 1 또는 -1의 위치에 따라 부분곱들을 시프트 하여 더할 때 모든 부분곱들의 부호확장이 필요하며 이로 인해 하드웨어의 오버헤드가 증가하게 된다. 본 논문에서는 부호확장 부분에서의 캐리 전파를 적절히 조절함으로써 부호확장으로 인한 오버헤드를 조절 할 수 있다는 사실을 이용하여 새로운 부호확장 오버혜드 감소방법을 제시한다. 제안한 방법과 기존의 방법을 다양한 시뮬레이션을 통해서 비교하고 기존의 방법에 비해 약 30%의 부호확장 오버헤드를 줄일 수 있음을 보인다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.27-30
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• 2002

10-bit 해상도, 10MS/s의 ADC를 Stage 당 1.5-Bit의 Resolution을 가지는 Redundant signed digit(RSD) 방식의 파이프라인 구조를 이용하여 설계하였다. Error Correction Logic을 사용함으로써 비교기를 Coarse하게 설계하였고 잔류 전압 증폭기의 최적 Scaling을 통하여 일반적인 ADC에 비해 성능 저하 없이 효율적으로 소비 전력을 감소시켰다. 또한, Charge Pump의 선택적 사용을 통해 기생 커패시턴스의 영향을 최소화함으로써 잔류전압 증폭기의 출력 전압 특성을 향상 시켰다. 삼성 0.35u CMOS 공정 파라미터를 이용하여 입력 전압 $-1{\sim}1V$, 공급 전압 $-1.5{\sim}1.5V$에서 18.73mW로 설계하였으며 HSPICE로 시뮬레이션 하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.