• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1C
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• pp.21-27
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• 2009

We present an efficient exponentiation algorithm for a finite field $GF(2^n)$ determined by an optimal normal basis of type II using signed digit representation of the exponents. Our signed digit representation uses a non-adjacent form (NAF) for $GF(2^n)$. It is generally believed that a signed digit representation is hard to use when a normal basis is given because the inversion of a normal element requires quite a computational delay. However our result shows that a special normal basis, called an optimal normal basis (ONB) of type II, has a nice property which admits an effective exponentiation using signed digit representations of the exponents.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.50-58
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• 2013

In this paper, parallel decimal fixed-point multiplier which uses the limited range of Singed-Digit number encoding and the reduction step is proposed. The partial products are generated without carry propagation delay by encoding a multiplicand and a multiplier to the limited range of SD number. With the limited range of SD number, the proposed multiplier can improve the partial product reduction step by increasing the number of possible operands for multi-operand SD addition. In order to estimate the proposed parallel decimal multiplier, synthesis is implemented using Design Compiler with SMIC 180nm CMOS technology library. Synthesis results show that the delay of proposed parallel decimal multiplier is reduced by 4.3% and the area by 5.3%, compared to the existing SD parallel decimal multiplier. Despite of the slightly increased delay and area of partial product generation step, the total delay and area are reduced since the partial product reduction step takes the most proportion.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• ETRI Journal
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• v.29 no.5
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• pp.619-632
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• 2007

Side channel attacks are a very serious menace to embedded devices with cryptographic applications. To counteract such attacks many randomization techniques have been proposed. One efficient technique in elliptic curve cryptosystems randomizes addition chains with binary signed digit (BSD) representations of the secret key. However, when such countermeasures have been used alone, most of them have been broken by various simple power analysis attacks. In this paper, we consider combinations which can enhance the security of countermeasures using BSD representations by adding additional countermeasures. First, we propose several ways the improved countermeasures based on BSD representations can be attacked. In an actual statistical power analysis attack, the number of samples plays an important role. Therefore, we estimate the number of samples needed in the proposed attack.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.987-990
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• 1998

An optical adder for a modified signed-digit(MSD) number system using joint spatial encoding method is proposed. In order to minimize the numbers of symbolic substitution rules, nine input patterns were divided into five groups of the same addition results. For recognizing the input reference patterns, masks and reference patterns without any other spatial operations are used. This adder is implemented by smaller system in size than a conventional adder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.31-38
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• 2012

In this paper, a low area timing synchronization structure for the IEEE 802.11a OFDM MODEM SoC is proposed. The timing synchronization block of the IEEE 802.11a OFDM MODEM SoC requires large implementation area. In the proposed timing synchronization structure, it is shown that the number of multiplication can be reduced by using the transposed direct form filter. Furthermore, implementation area of the proposed structure can be more reduced using CSD(Canonic Signed Digit) and Common Sub-expression Sharing techniques. Through Verilog-HDL coding and synthesis, it is shown that the 22.7 % of implementation area can be reduced compared with the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.43-51
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• 2004

An optical parallel modified signed-digit(MSD) number adder system is proposed by using triple rail-coding input patterns and serial arrangement method of symbolic substitution. By combing overlapped arithmetic results. which are produced by encoding MSD input as triple rail-coding patterns. into the same patterns, symbolic substitution rules are reduced and also by using serialized and space-shifted input patterns in optical experiments, the optical adder without space-shifting operation, NOR operation and threshold operation is implemented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• The Magazine of the IEIE
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• v.28 no.4
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• pp.103-104
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• 2001

• Journal of IKEEE
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• v.19 no.3
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• pp.342-348
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• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.