• ETRI Journal
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• v.34 no.2
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• pp.256-259
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• 2012

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.637-640
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• 2000

ERG signal represents the responses of the each layer of retina for the visual stimulus and accumulated responses according to the signal processing occurring in the retina. By investigating the reaction types of each wave of the ERG, various kinds of information for the diagnosis and the signal processing mechanisms in the retina can be obtained. In this paper, the ERG signal is generated by simulating of the volume conductor field of response of each retina layer and summing of them algebraically. The retina model used for simulation is Shah’s Computer Retina model which is one of the most reliable models recently developed. The generated ERG is compared with the typical ERG and shows a very close similarity. By changing the parameters of the retina model, the diagnostic investigation is performed with the variation of the ERG waveform.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2006.06a
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• pp.25-28
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• 2006

In this paper, we say the shading correction system supporting multi-resolution for camera. The shading effect is caused by non-uniform illumination, non-uniform camera sensitivity, or even dirt and dust on glass (lens) surfaces. In general this shading effect is undesirable [1]. Eliminating it is frequently necessary for subsequent processing and especially when quantitative microscopy is the fine goal. The proposed system is available on thirty nine kinds of image resolutions scanned by interlaced and progressive type. Moreover, the system is using various continuous quadratic equations instead of using the piece-wise linear curve which is composed of multiple line segments. Finally, the system could correct the correct effect without discontinuity in any image resolution. The proposed system is also experimentally demonstrated with Xilinx Virtex FPGA XCV2000E- 6BG5560 and the TV set.

• ETRI Journal
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• v.36 no.3
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• pp.506-509
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• 2014

This paper studies the energy efficiency power allocation for cognitive radio networks based on uplink orthogonal frequency-division multiplexing. The power allocation problem is intended to minimize the maximum energy efficiency measured by "Joule per bit" metric, under total power constraint and robust aggregate mutual interference power constraint. However, the above problem is non-convex. To make it solvable, an equivalent convex optimization problem is derived that can be solved by general fractional programming. Then, a robust energy efficiency power allocation scheme is presented. Simulation results corroborate the effectiveness of the proposed methods.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.3
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• pp.99-105
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• 2014

A graphic processing unit (GPU) can perform the same calculation on multiple data (SIMD: single instruction multiple data) using hundreds of to thousands of special purpose processors for graphic processing. Thus, high efficiency is expected when GPU is used for the generation and correlation of satellite navigation signals, which perform generation and processing by applying the same calculation procedure to tens of millions of discrete signal samples per second. In this study, the structure of a GPU-based GNSS simulator for the generation and processing of satellite navigation signals was designed, developed, and verified. To verify the developed satellite navigation signal generator, generated signals were applied to the OEM-V3 receiver of Novatel Inc., and the measured values were examined. To verify the satellite navigation signal processor, the performance was examined by collecting and processing actual GNSS intermediate frequency signals. The results of the verification indicated that satellite navigation signals could be generated and processed in real time using two GPUs.

• Journal of Information Processing Systems
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• v.8 no.4
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• pp.669-684
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• 2012

Discrete wavelet transforms are extensively preferred in biomedical signal processing for denoising, feature extraction, and compression. This paper presents a new denoising method based on the modeling of discrete wavelet coefficients of ECG in selected sub-bands with Kernel density estimation. The modeling provides a statistical distribution of information and noise. A Gaussian kernel with bounded support is used for modeling sub-band coefficients and thresholds and is estimated by placing a sliding window on a normalized cumulative density function. We evaluated this approach on offline noisy ECG records from the Cardiovascular Research Centre of the University of Glasgow and on records from the MIT-BIH Arrythmia database. Results show that our proposed technique has a more reliable physical basis and provides improvement in the Signal-to-Noise Ratio (SNR) and Percentage RMS Difference (PRD). The morphological information of ECG signals is found to be unaffected after employing denoising. This is quantified by calculating the mean square error between the feature vectors of original and denoised signal. MSE values are less than 0.05 for most of the cases.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.3 s.303
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• pp.121-128
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• 2005

On the research field for speech signal, neural network mainly uses for the category classification in speech recognition and applies to signal processing. Accordingly, this paper proposes a noise reduction system using a time-delay neural network, which implements the mapping from the space of speech signal degraded by noise to the space of clean speech signal. It is confirmed that this method is effective for speech degraded not only by white noise but also by colored noise using the noise reduction system, which restores the amplitude component of fast Fourier transform.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.109-114
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• 2004

This paper proposes an advanced circuit for the fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. We also propose an effective isolation strategy for removing noise and signal coupling of each sensor pixel. The fingerprint sensor circuit was designed and simulated, and the layout was performed.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.683-686
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• 1999

In this paper, we develop an active sonar signal synthesis model to analyze the detection performance of active sonar systems in a shallow water environment. Using this model, we synthesize the return signal of a bistatic sonar system at a typical operating frequency. This signal can be used to test proper active sonar signal processing techniques for real applications.