• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.2
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• pp.99-108
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• 2004

This thesis deals a method to deliver more realistic sound by cancelling the cross-talk which is inherent to the 5.1 channel speaker system. The acoustical model for cross-talk cancellation is the free field model. This model minimizes distortion of sound. I used the bark scale sound quality compensation which based on psycho-acoustic. For the surround channels, band-limited sound quality compensation is performed in the frequency domain. I also performed the sound quality assessment test on the traditional 2 channel stereo and 5.1 channel system. This test is performed in the test chamber which satisfies the ITU-R specifications. I uses the IACC(Inter-Aural Cross-Correlation) to determine the preferences of the amateur and the golden ear experts to asses the trans-aural filter. According to the result from the proposed method, I got more the 38㏈ separation rates with the Dolby standard speaker array. The results on the diffusion by the subjective test with the experts shows 0.4 point increased then before.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.15-22
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• 1998

The goal of this paper is to propose analyzing and evaluating method of power parameters for motor drive system with various experimental graphic screens and numerical results and to develop the proposed system. A developed system is made up 586-PC and DSP board, motor drive system, power parameters analyzing and evaluating software for windows. Power parameters are analyzed using correlation signal processing techniques based on the correlation between voltage and current waveforms. Analysis results are visualized by 3-D current coordinates, and it is compared and evaluated with conventional time/ frequency domain. To verify the validity of the proposed system, capacitor run type single phase induction motor and thyristor speed controller is used for analyzing. Power and harmonic parameters of motor drive system is analyzed and verified, with varying fire angle of thyristor speed controller, and the proposed approach is to confirm validity.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.188-198
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• 2010

Recently, as the demand of the environmental-friendly energy storage system such as an electric double-layer condenser increases, that of the bidirectional charger/discharger for the systems also increases. However, when charging/discharging mode-change occurs, the charger/discharger employing a bi-directional DC-DC converter with a commercialized analog controller has a complex circuit scheme, and a poor transient response. On the other hand, if a single digital controller is used for the bi-directional mode, the system performances can be improved by application of an advanced power-processing algorithm. In the paper, an environmental-friendly power storage systems including an Electric Double Layer Capacitor(EDLC) banks were developed with a bi-directional buck-boost converter and a digital signal processor (TMS320F28335). A simulation test-bed was realized and tested by MATLAB Simulink, and the hardware experiment was performed which shows that the dynamic response was improved such as the simulation results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.10
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• pp.22-29
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• 1998

In this paper, an 10 bit current-mode CMOS A/D converter with a current predictor is designed with a CMOS process to be integrated into a portable image signal processing system. A current predictor let the number of comparator reduce to 70 percent compared with the two step flash architecture. The current magnitude of current reference is reduced to 68 percent with a modular current reference. The designed 10 bit Low-power current-mode CMOS A/D converter with a current predictor is simulated with HSPICE using 0.6$\mu\textrm{m}$ N-well single-poly triple-metal CMOS process parameters. It results in a conversion rate of 10MSamples/s. A power consumption is measured to be 94.4mW at single +5V supply voltage. The 10 bit A/D converter fabricated using the same process occupies the chip area of 1.8mm x 2.4mm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.12
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• pp.165-170
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• 2005

In this paper, influences of a ultra wideband (UWB) antenna on impulse channel measurement are investigated in time domain (TD) and frequency domain (FD) as well. Firstly, impulse response of an UWB antenna is obtained and then using the result of impulse response of the UWB antenna, influences of the antenna on impulse radio channel is analyzed. Furthermore, using the impulse response of the UWB anenna, method of impulse radio channel analysis is presented by excluding the effect of the antenna from an impulse radio channel. For verifying the theory, a modified conical monopole antenna is designed for measuring impulse radio channel and its impulse response is obtained. After that, in order to investigate the effects of the UWB antenna on an impulse radio channel, multipath environments are set up in an anechonic chamber and transmission coefficient for each multipath environment is measured with an aid of vector network analyzer. Data measured in frequency domain is transformed into those in time domain by way of signal processing. Measurement shows that such properties of the antenna as dispersion and ringing affect impulse radio channel. Moreover, using the impulse response of the antenna, impulse response of only multipath channel is obtained.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.6
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• pp.38-43
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• 2009

We provide a method to infer finger flexing motions using a 4-channel surface electromyogram (sEMG). Surface EMGs are harmless to the human body and easily acquired. However, they do not reflect the activity of specific nerves or muscles, unlike invasive EMGs. On the other hand, the non-invasive type is difficult to use for discriminating various motions while using only a small number of electrodes. Surface EMG data in this study were obtained from four electrodes placed around the forearm. The motions were the flexion of the thumb, index, middle, ring, and little linger. One subject was trained with these motions and another left was untrained. The maximum likelihood estimation was used to infer the finger motion. Experimental results have showed that this method could be useful for recognizing finger motions. The average accuracy was as high as 95%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.6
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• pp.117-124
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• 2008

The approaches to overcome the limited spatial resolution and the limited dynamic range of image sensors have been studied independently. A high resolution image is reconstructed from multiple low resolution observations and a wide dynamic range image is reconstructed from differently exposed multiple low dynamic range in es based on signal processing approach. In practical situations, it is reasonable to address them in a unified context because the recorded image suffers from limitations of both spatial resolution and dynamic range. In this paper, the image acquisition process including limited spatial resolution and limited dynamic range is modelled. With the image acquisition model, the response function of the imaging system is estimated and the single image of which spatial resolution and dynamic range are simultaneously enhanced is obtained. Experimental results indicate that the proposed algorithm outperforms the conventional approaches that perform the high resolution and wide dynamic range reconstruction sequentially with respect to both objective and subjective criteria.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.141-146
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• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.