• Title/Summary/Keyword: Signal Transition Graph

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Synthesis of Asynchronous Circuits from C Language Using Syntax Directed Translation (구문중심적 변환을 통한 C언어의 비동기회로 합성기법)

  • 곽상훈;이정근;이동익
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.353-356
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    • 2002
  • Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

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Test Generation for Speed-Independent Asynchronous Circuits with Undetectable Faults Identification

  • Eunjung Oh;Lee, Dong-Ik;Park, Ho-Yong
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.359-362
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    • 2000
  • In this paper, we propose a test pattern generation algorithm on the basis of the identification of undetectable faults for Speed-Independent(SI) asynchronous control circuits. The proposed methodology generates tests from the specification of a target circuit, which describes the behavior of the circuit in the form of Signal Transition Graph (STG). The proposed identification method uses only topological information of a target circuit and reachability information of a fault-free circuit, which is generated in the form of Binary Decision Diagram(BDD) during pre-processing. Experimental results show that high fault coverage over single input stuck-at fault model is obtained for several synthesized SI circuits and the use of the identification process as a preprocessing decreases execution time of the proposed test generation with negligible costs.

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Flexible Partitioning of CDFGs for Compact Asynchronous Controllers

  • Sretasereekul, Nattha;Okuyama, Yuichi;Saito, Hiroshi;Imai, Masashi;Kuroda, Kenichi;Nanya, Takashi
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1724-1727
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    • 2002
  • Asynchronous circuits have the potential to solve the problems related to parameter variations such as gate delays in deep sub-micron technologies. However, current CAD tools for large-scale asyn-chronous circuits partition specification irrelevantly, because these tools cannot control the granularity of circuit decomposition. In this paper we propose a hierarchical Control/Data Flow Graph (CDFG) containing nodes that are flexibly partitioned or merged into other nodes. We show a partitioning algorithm for such CDFGs to generate handleable Signal Transition Graphs (STGs) for asynchronous synthesis tools. The algorithm a1lows designers to assign the maximum number of signals of partitioned nodes considering of timality. From an experiment, this algorithm can flexibly partition and result in more compact asynchronous controllers.

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