• Title/Summary/Keyword: Signal Processing Algorithm

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On a Pitch Alteration Method using Scaling the Harmonics Compensated with the Phase for Speech Synthesis (위상 보상된 고조파 스케일링에 의한 음성합성용 피치변경법)

  • Bae, Myung-Jin
    • The Journal of the Acoustical Society of Korea
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    • v.13 no.6
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    • pp.91-97
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    • 1994
  • In speech processing, the waveform codings are concerned with simply preserving the waveform of signal through a redundancy reduction process. In the case of speech synthesis, the waveform codings with high quality are mainly used to the synthesis by analysis. Because the parameters of this coding are not classified as both excitation and vocal tract, it is difficult to apply the waveform coding to the synthesis by rule. Thus, in order to apply the waveform coding to synthesis by rule, it is necessary to alter the pitches. In this paper, we proposed a new pitch alteration method that can change the pitch period in waveform coding by dividing the speech signals into the vocal tract and excitation parameters. This method is a time-frequency domain method preserving the phase component of the waveform in time domain and the magnitude component in frequency domain. Thus, it is possible that the waveform coding is carried out the synthesis by rule in speech processing. In case of using the algorithm, we can obtain spectrum distortion with $2.94\%$. That is, the spectrum distortion is decreased more $5.06\%$ than that of the pitch alteration method in time domain.

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Video Coding Method Using Visual Perception Model based on Motion Analysis (움직임 분석 기반의 시각인지 모델을 이용한 비디오 코딩 방법)

  • Oh, Hyung-Suk;Kim, Won-Ha
    • Journal of Broadcast Engineering
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    • v.17 no.2
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    • pp.223-236
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    • 2012
  • We develop a video processing method that allows the more advanced human perception oriented video coding. The proposed method necessarily reflects all influences by the rate-distortion based optimization and the human visual perception that is affected by the visual saliency, the limited space-time resolution and the regional moving history. For reflecting the human perceptual effects, we devise an online moving pattern classifier using the Hedge algorithm. Then, we embed the existing visual saliency into the proposed moving patterns so as to establish a human visual perception model. In order to realize the proposed human visual perception model, we extend the conventional foveation filtering method. Compared to the conventional foveation filter only smoothing less stimulus video signals, the developed foveation filter can locally smooth and enhance signals according to the human visual perception without causing any artifacts. Due to signal enhancement, the developed foveation filter more efficiently transfers the bandwidth saved at smoothed signals to the enhanced signals. Performance evaluation verifies that the proposed video processing method satisfies the overall video quality, while improving the perceptual quality by 12%~44%.

Improvement of Positioning Performance for GPS Module(KGP9800C) (GPS모듈(KGP9800C)의 측위성능개선)

  • 신형일;김형석;김석재;배문기;박노선
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.37 no.3
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    • pp.181-189
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    • 2001
  • This paper describes the positioning accuracy of GPS moduls (KGP9800C, KiRyung) which need to record the operating position of fishing boat as realtime processing in order to develope auto recording system of fishing boat's operating information, and then it's positioning accuracy for DGPS receiver (MGP-100D, Shin-A) and DGPS beacon (GP-36, Furuno) were analyzed. Futhermore, it was examined the positioning error of the GPS module with processing algorithm to minimize the effect of the signal fluctuations. The results indicate that the positioning error is able to decrease 5m as 2drms, and such improvement of positioning performance for GPS module (KGP9800C) can be provide the basic design data in the development of the auto recording system of fishing boat's operating information.

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Recognition Model of the Vehicle Type usig Clustering Methods (클러스터링 방법을 이용한 차종인식 모형)

  • Jo, Hyeong-Gi;Min, Jun-Yeong;Choe, Jong-Uk
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.2
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    • pp.369-380
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    • 1996
  • Inductive Loop Detector(ILD) has been commonly used in collecting traffic data such as occupancy time and non-occupancy time. From the data, the traffic volume and type of passing vehicle is calculated. To provide reliable data for traffic control and plan, accuracy is required in type recognition which can be utilized to determine split of traffic signal and to provide forecasting data of queue-length for over-saturation control. In this research, a new recognition model issuggested for recognizing typeof vehicle from thecollected data obtained through ILD systems. Two clustering methods, based on statistical algorithms, and one neural network clustering method were employed to test the reliability and occuracy for the methods. In a series of experiments, it was found that the new model can greatly enhance the reliability and accuracy of type recongition rate, much higher than conventional approa-ches. The model modifies the neural network clustering method and enhances the recongition accuracy by iteratively applying the algorithm until no more unclustered data remains.

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SoC Design of Speaker Connection System by Efficient Cosimulation (효율적인 통합시뮬레이션에 의한 스피커 연결 시스템의 SoC 설계)

  • Song, Moon-Vin;Song, The-Hoon;Oh, Chae-Gon;Chung, Yun-Mo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.68-73
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    • 2006
  • This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

Detection of Traffic Light using Color after Morphological Preprocessing (형태학적 전처리 후 색상을 이용한 교통 신호의 검출)

  • Kim, Chang-dae;Choi, Seo-hyuk;Kang, Ji-hun;Ryu, Sung-pil;Kim, Dong-woo;Ahn, Jae-hyeong
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2015.05a
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    • pp.367-370
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    • 2015
  • This paper proposes an improve method of the detection performance of traffic lights for autonomous driving cars. Earlier detection methods used to adopt color thresholding, template matching and based learning maching methods, but its have some problems such as recognition rate decreasing, slow processing time. The proposed method uses both detection mask and morphological preprocessing. Firstly, input color images are converted to YCbCr image in order to strengthen its illumination, and horizontal edge components are extracted in the Y Channel. Secondly, the region of interest is detected according to morphological characteristics of the traffic lights. Finally, the traffic signal is detected based on color distributions. The proposed method showed that the detection rate and processing time improved rather than the conventional algorithm about some surrounding environments.

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SHA-1 Pipeline Configuration According to the Maximum Critical Path Delay (최대 임계 지연 크기에 따른 SHA-1 파이프라인 구성)

  • Lee, Je-Hoon;Choi, Gyu-Man
    • Convergence Security Journal
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    • v.16 no.7
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    • pp.113-120
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    • 2016
  • This paper presents a new high-speed SHA-1 pipeline architecture having a computation delay close to the maximum critical path delay of the original SHA-1. The typical SHA-1 pipelines are based on either a hash operation or unfolded hash operations. Their throughputs are greatly enhanced by the parallel processing in the pipeline, but the maximum critical path delay will be increased in comparison with the unfolding of all hash operations in each round. The pipeline stage logics in the proposed SHA-1 has the latency is similar with the result of dividing the maximum threshold delay of a round by the number of iterations. Experimental results show that the proposed SHA-1 pipeline structure is 0.99 and 1.62 at the operating speed ratio according to circuit size, which is superior to the conventional structure. The proposed pipeline architecture is expected to be applicable to various cryptographic and signal processing circuits with iterative operations.

A Study on Modified Weighted Filter for Edge Preservation in AWGN Environments (AWGN 환경에서 에지 보존을 위한 변형된 가중치 필터에 관한 연구)

  • Kwon, Se-Ik;Hwang, Yeong-Yeun;Kim, Nam-Ho
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.05a
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    • pp.661-663
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    • 2016
  • Corruption occurs in the process of processing image signal and the corruption changes the pixel value within the image to damage the original information. AWGN(additive white Gaussian noise) is a representative example. For filters to remove AWGN, there are filters such as MF(mean filter), WF(wiener filter), and AWMF(adaptive weighted mean filter). However images processed through standard previous filters lock preservation characteristics in edge areas. Therefore, threshold value is applied for processing on the standard deviation of the local mask in this study and if the standard deviation is smaller than the threshold value, it is not filtered and if the value is bigger than the threshold value, the study suggested an algorithm that processes using weighted value utilizing standard deviation.

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Implementation of Telematics System Using Driving Pattern Detection Algorithm (운전패턴 검출 알고리즘을 적응한 텔레매틱스 단말기 구현)

  • Kin, Gi-Seok;Jung, Hee-Seok;Yun, Kee-Bang;Jeong, Kyung-Hoon;Kim, Ki-Doo
    • 전자공학회논문지 IE
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    • v.45 no.4
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    • pp.33-41
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    • 2008
  • Telematics system includes the "vehicle remote diagnosis technology", "driving pattern analysis technology" which are commercially attractive in the real life. To implement those technologies, we need vehicle signal interface, vehicle diagnosis interface, accelerometer/yaw-rate sensor interface, GPS data processing, driving pattern analysis, and CDMA data processing technique. Based on these technologies, we analyze the error existence by diagnosing the EMS(Engine Management System), TMS(Transmission Management System), ABS/TCS, A/BAG in real time. And we are checking about a driving pattern and management of the vehicle, which are sent to the information center through the wireless communication. These database results will make the efficient vehicle and driver management possible. We show the effectiveness of our results by field driving test after completing the H/W & S/W design and implementation for vehicle remote diagnosis and driving pattern analysis.

Hardware Implementation of Motor Controller Based on Zynq EPP(Extensible Processing Platform) (Zynq EPP를 이용한 모터 제어기의 하드웨어 구현)

  • Moon, Yong-Seon;Lim, Seung-Woo;Lee, Young-Pil;Bae, Young-Chul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.11
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    • pp.1707-1712
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    • 2013
  • In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.