• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.10a
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• pp.67-73
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• 2006

A system in package (SiP) generally contains a variety of systems such as analog, digital, optical and micro-electro-mechanical systems, integrated in a system-level package connected through a substrate. However, there are many electrical and mechanical reliability issues including the reliability issue for embedded structures. A mismatch of thermal coefficients of expansion among packaging materials and devices can lead to warping or delamination in the package. In this study, the effect of material properties of underfill, such as Young's modulus and CTE, are investigated through FEM simulation. Experimental investigation on the warpage of the package is also carried out to verify the simulation results. The results show that the reliability of the system in package is closely related to the material properties of underfill. The results of this study provide a good guidance for the material selection when designing the system in package.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.207-208
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• 2008

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.11 s.114
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• pp.1105-1111
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• 2006

In this paper, using low-temperature co-fired ceramic(LTCC) based system-in-package(SiP) technology, a very compact power amplifier LTCC module was designed, fabricated, and then characterized for 60 GHz wireless transmitter applications. In order to reduce the interconnection loss between a LTCC board and power amplifier monolithic microwave integrated circuits(MMIC), bond-wire transitions were optimized and high-isolated module structure was proposed to integrate the power amplifier MMIC into LTCC board. In the case of wire-bonding transition, a matching circuit was designed on the LTCC substrate and interconnection space between wires was optimized in terms of their angle. In addition, the wire-bonding structure of coplanar waveguide type was used to reduce radiation of EM-fields due to interconnection discontinuity. For high-isolated module structure, DC bias lines were fully embedded into the LTCC substrate and shielded with vias. Using 5-layer LTCC dielectrics, the power amplifier LTCC module was fabricated and its size is $4.6{\times}4.9{\times}0.5mm^3$. The fabricated module shows the gain of 10 dB and the output power of 11 dBm at P1dB compression point from 60 to 65 GHz.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.43-48
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• 2016

3-Dimensional System in Package (3-D SiP) structure (Amkor calls it mPossum-molded Possum) using double side Surface Mount Technology (SMT) and double side molding was evaluated in order to achieve small/thin form factor as well as good functionality by integration and double side layout. As the new platform on laminate substrate basis, molding process was challenge in mold flow balance at top and bottom side and package warpage control over the overall assembly process. There were two types of different molding process evaluated with 1) 1-step molding which was done at both side at the same time and 2) 2-step molding which was done at the conventional molding process twice. Mold simulation helped to narrow down the material selections and parameters available before actual sample build. There were many challenges for this first trial in design/ parameter and material types but optimized them to enable this structure.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.229-237
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• 2011

In this paper, a 60 GHz LTCC SiP with low-power CMOS OOK modulator and demodulator is presented. The 60 GHz modulator is designed in a 90-nm CMOS process. The modulator uses a current reuse technique and only consumes 14.4-mW of DC power in the on-state. The measured data rate is up to 2 Gb/s. The 60 GHz OOK demodulator is designed in a 130nm CMOS process. The demodulator consists of a gain boosting detector and a baseband amplifier, and it recovers up to 5 Gb/s while consuming low DC power of 14.7 mW. The fabricated 60 GHz modulator and demodulator are fully integrated in an LTCC SiP with 1 by 2 patch antenna. With the LTCC SiP, 648 Mb/s wireless video transmission was successfully demonstrated at wireless distance of 20-cm.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.14-23
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• 2010

This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.