• Composites Research
• /
• v.35 no.1
• /
• pp.23-30
• /
• 2022

Polycarbosilane(PCS) is an important precursor for melt-spinning the silicon carbide(SiC) fibers and manufacturing ceramics. The PCS is a metal-organic polymer precursor capable of producing continuous SiC fibers having excellent performance such as high-temperature resistance and oxidation resistance. The SiC fibers are manufactured through melt-spinning, stabilization, and heat treatment processes using the PCS manufactured by synthesis, purification, and control of the molecular structure. In this paper, we analyzed the effect of purification of unreacted substances and low molecular weight through solvent treatment of PCS and the effect of heat treatment at various temperatures change the polymerization and network rearrangement of PCS. Especially, we investigated the complex viscosity and structural arrangement of PCS precursors according to solvent treatment and heat treatment through the rheological properties.

• Journal of the Microelectronics and Packaging Society
• /
• v.30 no.1
• /
• pp.63-70
• /
• 2023

Today, the importance of power semiconductors continues to increase due to serious environmental pollution and the importance of energy. Particularly, SiC-MOSFET, which is one of the wide bandgap (WBG) devices, has excellent high voltage characteristics and is very important. However, since the electrical properties of SiC-MOSFET are heatsensitive, thermal management through a package is necessary. In this paper, we propose an insulated metal substrate (IMS) method rather than a direct bonded copper (DBC) substrate method used in conventional power semiconductors. IMS is easier to process than DBC and has a high coefficient of thermal expansion (CTE), which is excellent in terms of cost and reliability. Although the thermal conductivity of the dielectric film, which is an insulating layer of IMS, is low, the low thermal conductivity can be sufficiently overcome by allowing a process to be very thin. Electric-thermal co-simulation was carried out in this study to confirm this, and DBC substrate and IMS were manufactured and experimented for verification.

• Journal of the Korean Magnetics Society
• /
• v.17 no.2
• /
• pp.95-98
• /
• 2007

In this paper, the magnetic properties and the annealing behavior of spin valve structures with Mo(MoN) underlayers were studied for various underlayer thickness. The spin valve structure was Si substrate/Mo(MoN)$(t{\AA})/NiFe(21{\AA})/CoFe(28{\AA})/Cu(22{\AA})/CoFe(18{\AA})/IrMn(65{\AA})/Ta(25 {\AA})$. Mo and MoN films were deposited on Si substrates and their thermal annealing behavior was analyzed. The deposition rate of the MoN thin film was decreased and tile resistivity of the MoN thin films were increased as the $N_2$ gas flow was increased. The variations of MR ratio and magnetic exchange coupling field of spin valve structure were smaller with MoN underlayers than that with Mo underlayers up to thickness of $51{\AA}$. MR ratio of spin valves with Mo underlayers was 2.86% at room temperature and increased up to 2.91 % after annealing at $200^{\circ}C$. Upon annealing at $300^{\circ}C$, the MR ratio decreased about 2.16%. The MR ratio of spin valves structure with MoN underlayers for $N_2$ gas flow 1 sccm was 5.27% at room temperature and increased up to 5.56% after annealing at $200^{\circ}C$. Upon annealing at $300^{\circ}C$, the MR ratio decreased about 4.9%.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.645-647
• /
• 2008

In this paper, we analyzed interface trap density between pentacene and PVP and SiO2 gate dielectric by using high-low C-V characteristics. The interface trap density was $10^{13}\;cm^{-2}eV^{-1}$.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.155-157
• /
• 1991

This paper describe a Laser CVD technology which realizes planarized interlevel dielectrics in sub-micron VLSI's. This technology comprises sub-micron gap filling with $SiO_2$ films between metal lines. Laser CVD process conditions have been investigated to improve step coverage of interlevel dielectrics. An ArF(193nm) Excimer Laser was used to excite and dissociate gas phase $SiH_4\;and\;N_2O$ molecules. The Laser CVD by $N_2O\;and \;SiH_4$. mixture gases has realized conformal deposition above the temperature of $300^{\circ}C$, as a result sub-micron gaps were buried with $SiO_2$ films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.365-365
• /
• 2010

In this paper, silicon nitride thin films with different silane and ammonia gas ratios were deposited and characterized for the antireflection and passivation layer of high efficiency single crystalline silicon solar cells. As the flow rate of the ammonia gas increased, the refractive index decreased and the band gap increased. Consequently, the transmittance increased due to the higher band gap and the decrease of the defect states which existed for the 1.68 and 1.80 eV in the SiNx films. The reduction in the carrier lifetime of the SiNx films deposited by using a higher $NH_3/SiH_4$ flow ratio was caused by the increase of the interface traps and the defect states in/on the interface between the SiNx and the silicon wafer. The silicon and nitrogen rich films are not suitable for generating both higher carrier lifetimes and transmittance. These results indicate that the band gap and the defect states of the SiNx films should be carefully controlled in order to obtain the maximum efficiency for c-Si solar cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.6
• /
• pp.580-585
• /
• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Nuclear Engineering and Technology
• /
• v.38 no.7
• /
• pp.675-680
• /
• 2006

The neutron transmutation doping of silicon (NTD), as a method to produce a high quality semiconductor, utilizes the transmutation of a silicon element into phosphorus by neutron absorption in a silicon single crystal. In this paper, we present the design of a neutron screen for a 6' Si ingot irradiation in the NTD2 hole of HANARO. The goal of the design is to achieve an even flat axial distribution of the resistivity, or $Si^{30}(n,{\gamma})Si^{31}$ reaction rate, in the irradiated Si ingot. We used the MCNP4C code to simulate the neutron screen and to calculate the reaction rate distribution in the Si ingot. The fluctuations in the axial distribution were estimated to be within ${\pm}2.0%$ from the average for the final neutron screen design; thus, they satisfy the customers' requirement for uniform irradiation. On the other hand, we determined the optimal insertion depths of the Si ingots by varying the critical control rod position, which greatly affects the axial flux distribution.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.305-310
• /
• 2013

In this paper, the pressure sensor usable in a high temperature, using a SDB(silicon-direct-bonding) wafer of Si/$SiO_2$/Si-sub structure was provided and studied the characteristic thereof. The pressure sensor produces a piezoresistor by using a single crystal silicon as a first layer of SDB wafer, to thus provide a prominent sensitivity, and dielectrically isolates the piezoresistor from a silicon substrate by using a silicon dioxide layer as a second layer thereof, to be thus usable even under the high temperature over $120^{\circ}C$ as a limited temperature of a general silicon sensor. The measured result for a pressure sensitivity of the pressure sensor has a characteristic of high sensitivity, and its tested result for an output of the sensor further has a very prominent linearity and hysteresis characteristic.

• Journal of Sensor Science and Technology
• /
• v.11 no.1
• /
• pp.54-59
• /
• 2002

This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.