• Advances in nano research
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• v.2 no.1
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• pp.23-56
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• 2014

The significant growth of the Si photovoltaic industry has been so far limited due to the high cost of the Si photovoltaic system. In this regard, the most expensive factors are the intrinsic cost of silicon material and the Si solar cell fabrication processes. Conventional Si solar cells have p-n junctions inside for an efficient extraction of light-generated charge carriers. However, the p-n junction is normally formed through very expensive processes requiring very high temperature (${\sim}1000^{\circ}C$). Therefore, several systems are currently under study to form heterojunctions at low temperatures. Among them, carbon nanotube (CNT)/Si hybrid solar cells are very promising, with power conversion efficiency up to 15%. In these cells, the p-type Si layer is replaced by a semitransparent CNT film deposited at room temperature on the n-doped Si wafer, thus giving rise to an overall reduction of the total Si thickness and to the fabrication of a device with cheaper methods at low temperatures. In particular, the CNT film coating the Si wafer acts as a conductive electrode for charge carrier collection and establishes a built-in voltage for separating photocarriers. Moreover, due to the CNT film optical semitransparency, most of the incoming light is absorbed in Si; thus the efficiency of the CNT/Si device is in principle comparable to that of a conventional Si one. In this paper an overview of several factors at the basis of this device operation and of the suggested improvements to its architecture is given. In addition, still open physical/technological issues are also addressed.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.156-160
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• 2006

Capacitance versus voltage (C-V) curves of Ge-nanocrystal (NC)-embedded MOS capacitors with and without a single capping Al2O3 layer are characterized in this work. C-V curves of the Ge-NC-embedded MOS capacitor with the A12O3 layer are counterclockwise in the voltage sweeps, which indicates tile presence of charge storages in the Ge NCs by the tunnelling of charge carriers between the Si substrate and the Ge NCs. In the Ge-NC-embedded MOS capacitor without Al2O3 layer, clockwise hysteresis of the C-V curves and leftward shifts of the flat band voltages are observed for the embedded MOS capacitor without the Al2O3 layer. It is suggested that the characteristics of the C-V curves are due to the charge trapping at oxygen vacancies within a SiO2 layer. In addition, the illumination of the white light enhances the lower capacitance part of the C-V hysteresis. The origin for the enhancement is discussed in this paper.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1928-1930
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• 1999

This paper describes on the growth of a ${\mu}c$-Si:H film on low cost substrate like glass by Hot Wire CVD method. The ${\mu}c$-Si:H film, prepared in 50mTorr pressure, $1800^{\circ}C$ wire temperature, and $H_2/SiH_4$ 10 showed three clear peaks. (111), (220), and (311) in X-ray spectroscopy. The crystallite size and crystalline volume fraction, calculated from Raman spectroscopy, was about 6nm and 70%, respectively. The FTIR transmission spectra of the film showed a different absorption peak with a-Si:H film around $2000-2100cm^{-1}$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.29-33
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• 2000

This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.4
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• pp.385-390
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• 2023

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.4
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• pp.360-368
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• 2017

This paper proposes the 80-kW high-efficiency bidirectional hybrid SiC boost/buck converter using droop control for DC nano-grid. The proposed converter consists of four 20-kW modules to achieve fault tolerance, ease of thermal management, and reduced component stress. Each module is constructed as a cascaded structure of the two basic bi-directional converters, namely, interleaved boost and buck converters. A six-pack hybrid SiC intelligent power module (IPM) suitable for the proposed cascaded structure is adopted for high-efficiency and compactness. The proposed converter with hybrid switching method reduces the switching loss by minimizing switching of insulated gate bipolar transistor (IGBT). Each module control achieves smooth transfer from buck to boost operation and vice versa, since current controller switchover is not necessary. Furthermore, the proposed parallel control using DC droop with secondary control, enhances the current sharing accuracy while well regulating the DC bus voltage. A 20-kW prototype of the proposed converter has been developed and verified with experiments and indicates a 99.3% maximum efficiency and 98.8% rated efficiency.

• Journal of the Korean Society for Precision Engineering
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• v.27 no.7
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• pp.117-122
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• 2010

Recently, aspheric glass lens molding core is fabricated with tungsten carbide(WC). If molding core is fabricated with silicon carbide(SiC), SiC coating process, which must be carried out before the Diamond-Like Carbon(DLC) coating can be eliminated and thus, manufacturing time and cost can be reduced. Diamond Like Carbon(DLC) is being researched in various fields because of its high hardness, high elasticity, high durability, and chemical stability and is used extensively in several industrial fields. Especially, the DLC coating of the molding core surface used in the fabrication of a glass lens is an important technical field, which affects the improvement of the demolding performance between the lens and molding core during the molding process and the molding core lifetime. Because SiC is a material of high hardness and high brittleness, it can crack or chip during grinding. It is, however, widely used in many fields because of its superior mechanical properties. In this paper, the grinding condition for silicon carbide(SiC) was developed under the grinding condition of tungsten carbide. A silicon carbide molding core was fabricated under this grinding condition. The measurement results of the SiC molding core were as follows: PV of 0.155 ${\mu}m$(apheric surface) and 0.094 ${\mu}m$(plane surface), Ra of 5.3 nm(aspheric surface) and 5.5 nm(plane surface).

• Journal of IKEEE
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• v.23 no.3
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• pp.832-838
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• 2019

In this paper, 4H-SiC MOSFET, the next generation power semiconductor device, was studied. In particular, Semi-SJ MOSFET structures with improved electrical characteristics than conventional DMOSFET structures were proposed in the class of 3300V, and static characteristics of conventional and proposed structures were compared and analyzed through TCAD simulations. Semi-SuperJunction MOSFET structure is partly structure that introduces SuperJunction, improves Electric field distribution through the two-dimensional depletion effect, and increases breakdown voltage. Benefit from the improvement of breakdown voltage, which can improve the on resistance as high doping is possible. The proposed structure has a slight reduction in breakdown voltage, but has an 80% decrease in on resistance compared to the conventional DMOSFET structure, and a 44% decrease in on resistance compared to the Current Spreading Layer(CSL) structure that improves the conventional DMOSFET structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.65-66
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• 1994

This paper describes study on the preparation of ferrite powder for bonded mallets. The specimen which has the basic composition of SrO$.$nF$_2$O$_3$ with n=5.9 is in nonstoichiomatric region. Calcination is performed under N$_2$ atmosphere 1175$^{\circ}C$, 1200$^{\circ}C$, 1225$^{\circ}C$, 1250$^{\circ}C$ and 1275$^{\circ}C$ respectively. Then, Cooling is carried out in the furnace. In order to increase coecivity and obtain uniform grain size, we add to the specimen 0.7wt%CaCO$_3$, 0.3wt % SiO$_2$, 0.5wt%Na$_2$SiO$_3$ and 0.5wr% Al$_2$O$_3$. Also, in order to increase milling effect, carbon coating on sample particles is tried. As the result, single magnetic domain partic1e with Size of 1$\mu\textrm{m}$ in obtained and magnetic properties are improved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.325-329
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• 1998

In this paper, the (Sr$_{1-x}$ Ca$_{x}$)TiO$_3$(SCT) thin films were deposited at various substrate temperature using RF magnetron sputtering method on optimized Pt-coated electrodes (Pt/TiN/SiO$_2$/Si). An influence of substrate temperature and annealing temperature on the structural and dielectric properties are investigated. The substrate temperature changed from 100[$^{\circ}C$] to 500[$^{\circ}C$] and crystalline SCT thin films were deposited abode 400[$^{\circ}C$]. All thin films had (111) preferred orientation, the (100) oriented films were obtained at the substrate temperature above 400[$^{\circ}C$]. The dielectric constant changes almost linearly in the temperature region of -80~+90[$^{\circ}C$], the temperature characteristics of the dielectric loss exhibited a stable value within 0.1, then not affected by substitutional contents. The capacitance characteristics appears a stable value within $\pm$5[%].