• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1297-1298
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• 2006

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have been attracted recently attention due to their highdevice performance expected from theoretical simulations among nanowire-based FETs with other gate geometries. OSG FETs with the channels of ZnO nanowires were successfully fabricated in this study with photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels of ZnO nanowires with diameters of about 60 nm are coated surroundingly by $Al_{2}O_{3}$ as gate dielectrics with atomic layer deposition. About 80 % of the surfaces of the nanowires coated with $Al_{2}O_{3}$ is covered with gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 98.9 $cm^{2}/Vs$, a peak transconductance of 0.4 ${\mu}S$, and an Ion/Ioff ratio of $10^6$ the value of the Ion/Ioff ratio obtained from this OSG FET is the highest among nanowire-based FETs, to our knowledge. Its mobility, peak transconductance, and Ion/Ioff ratio arc remarkably enhanced by 11.5, 32, and $10^6$ times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.

• 한국재료학회지
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• 제19권1호
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• pp.33-36
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• 2009

Inorganic-organic composite thin-film-transistors (TFTs) of ZnO nanowire/Poly(3-hexylthiophene) (P3HT) were investigated by changing the nanowire densities inside the composites. Crystalline ZnO nanowires were synthesized via an aqueous solution method at a low temperature, and the nanowire densities inside the composites were controlled by changing the ultrasonifiaction time. The channel layers were prepared with composites by spin-coating at 2000 rpm, which was followed by annealing in a vacuum at $100^{\circ}C$ for 10 hours. Au/inorganic-organic composite layer/$SiO_2$ structures were fabricated and the mobility, $I_{on}/I_{off}$ ratio, and threshold voltage were then measured to analyze the electrical characteristics of the channel layer. Compared with a P3HT TFT, the electrical properties of TFT were found to be improved after increasing the nanowire density inside the composites. The mobility of the P3HT TFT was approximately $10^{-4}cm^2/V{\cdot}s$. However, the mobility of the ZnO nanowire/P3HT composite TFT was increased by two orders compared to that of the P3HT TFT. In terms of the $I_{on}/I_{off}$ ratio, the composite device showed a two-fold increase compared to that of the P3HT TFT.

• 대한기계학회논문집B
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• 제39권10호
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• pp.825-829
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• 2015

나노선에서 코어-셸 헤테로 구조를 도입함으로써 열 전도율을 낮출 수 있으며, 이로 인해 열전 효율(ZT)을 향상시킬 수 있다는 것이 이론 연구를 통해 제안되었다. 본 논문에서는 코어-셸 나노선의 열전도율 감소를 실험적인 방법을 통해 확인하였다. 화학증기 증착법을 통해 만든 게르마늄-규소 $_x$ 게르마늄 $_{1-x}(Ge-Si_xGe_{1-x})$ 코어-셸 나노선의 열전도율을 마이크로 크기의 뜬 디바이스를 이용하여 측정하였다. 셸에서 측정된 실리콘의 함유율(x)는 0.65 로 확인하였으며, 게르마늄은 코어와 셸 사이에서, 격자 불일치(lattice mismatch)에서 비롯된 결점(defect)와 같은 역할을 한다. 또한, 4-point I-V 측정실험에, 휘트스톤 브릿지 실험을 추가 진행함으로써 측정 민감도를 강화하였다. 측정된 열전도율은 상온에서 9~13 W/mK 으로써, 비슷한 지름을 가지는 게르마늄 나노선과 비교하였을 때, 열전도율이 약 30 % 낮아졌음을 확인하였다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.142.2-142.2
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• 2018

One-dimensional metal oxide nanostructures have attracted considerable research activities owing to their strong application potential as components for nanosize electronic or optoelectronic devices utilizing superior optical and electrical properties. In which, semiconducting $SnO_2$ material with wide-bandgap Eg = 3.6 eV at room temperature, is one of the attractive candidates for optoelectronic devices operating at room temperature [1, 2], gas sensor [3, 4], and transparent conducting electrodes [5]. The synthesis and gas sensing properties of semiconducting $SnO_2$ nanomaterials have become one of important research issues since the first synthesis of SnO2 nanowires. In this study, $SnO_2$ nanowire networks were synthesized on a basis of a two-step process. In step 1, Sn spheres (30-800 nm in diameter) embedded in $SiO_2$ on a Si substrate was synthesized by a chemical vapor deposition method at $700^{\circ}C$. In step 2, using the source of these Sn spheres, $SnO_2$ nanowire (20-40 nm in diameter; $1-10{\mu}m$ in length) networks on a spherical Sn surface were synthesized by a thermal oxidation method at $800^{\circ}C$. The Au layers were pre-deposited on the surface of Sn spherical and subsequently oxidized Sn surface of Sn spherical formed SnO2 nanowires networks. Field emission scanning electron microscopy and high-resolution transmission electron microscopy images indicated that $SnO_2$ nanowires are single crystalline. In addition, the $SnO_2$ nanowire is also a tetragonal rutile, with the preferred growth directions along [100] and a lattice spacing of 0.237 nm. Subsequently, the $NO_2$ sensing properties of the $SnO_2$ network nanowires sensor at an operating temperature of $50-250^{\circ}C$ were examined, and showed a reversible response to $NO_2$ at various $NO_2$ concentrations. Finally, details of the growth mechanism and formation of Sn spheres and $SnO_2$ nanowire networks are also discussed.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2001년도 제21회 학술발표회 초록집
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• pp.134-134
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• 2001

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.200-200
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• 2009

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제37회 하계학술대회 초록집
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• pp.84-84
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• 2009

• 한국재료학회:학술대회논문집
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• 한국재료학회 2005년도 춘계학술발표대회 및 제8회 신소재 심포지엄 논문개요집
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• pp.161-161
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• 2005

• 한국진공학회:학술대회논문집
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• 한국진공학회 2004년도 제26회 학술발표회 초록집
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• pp.104-104
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• 2004

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.22.2-22.2
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• 2011

Si 나노와이어를 합성하는 다양한 방법들 중에서 Si 기판을 나노와이어 형태로 제작하는 무전해 식각법은 쉽고 간단하기 때문에 최근 많은 연구가 진행되고 있다. 무전해 식각법을 이용한 Si 나노와이어는 p 또는 n형의 전기적 특성을 갖는 Si 기판의 도핑농도에 따라 원하는 전기적 특성을 갖는 나노와이어를 얻을 수 있을 것이라는 기대가 있었지만 n형으로 제작된 나노와이어의 경우 식각에 의한 표면의 거칠기 때문에 그 특성을 나타내지 못하는 문제점을 가지고 있다. 본 연구에서는 무전해 식각법을 이용하여 p와 n형 나노와이어를 합성하고 field-effect transistors (FETs) 소자를 제작하여 각각의 특성을 구현하였다. 나노와이어와 절연막 사이의 계면 결함을 최소화하기 위하여 poly-4-vinylphenol (PVP) 고분자 절연막에 나노와이어를 삽입시킨 형태로 소자를 제작하였고, 특히 n형 나노와이어의 표면을 보다 평평하게 하기 위하여 열처리를 진행 하였다. 이렇게 각각의 특성이 구현된 나노와이어를 이용하여 soft-lithography 공정을 통해 complementary metal-oxide semiconductor (CMOS) 구조의 인버터 소자를 제작하였으며 그 전기적 특성을 평가하였다.