• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• Korean Journal of Materials Research
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• v.4 no.4
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• pp.416-427
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• 1994

The changes of crystallinity and microstructure and the $Si_{1-x}Ge_x/Sio_2$ interfaces of $Si_{1-x}Ge_x$ alloys deposited on amorphous $SiO_{2}$ were studied as a function of deposition temperature. The crystallinity, microstructure, and compositional uniformity of $Si_{1-x}Ge_x$ alloys deposited on the SiOl at different temperature were investigated by X-ray diffraction and transmission electron microscopy. And $Si_{1-x}Ge_x/Sio_2$ interface were investigated by high-resolution transmission electron microscopy. The $Si_{0.7}Ge_{0.3}/Sio_2$ films were deposited on amorphous $SiO_{2}$ at $300^{\circ}C,400^{\circ}C,500^{\circ}C,600^{\circ}C,$ and $700^{\circ}C$ by Si-MBE. In the film deposited at $300^{\circ}C$, only amorphous phase were observed. In the film deposited at $400^{\circ}C$, both amorphous and polycrystalline films were observed. Both phases were deposited simultaneously, but, at initial film growth, amorphous phase prevailed over polycrystalline phase. As the film thickness increased, the fraction of polycrystalline phase increased. At $500^{\circ}C$, thin amorphous layer was observed at lOnm from $SiO_{2}$ surface. In the films deposited at higher than $600^{\circ}C$, only crystalline phase were observed. Polycrystalline films had columnar structure. Compositional uniformity for deposited films were good regardless of deposition temperature. The interfaces of $Si_{1-x}Ge_x/Sio_2$ were flat, whatever polycrystal or amorphous was deposited on $SiO_{2}$.

• Korean Journal of Materials Research
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• v.19 no.12
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• pp.699-702
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• 2009

Due to the importance of the SiGe/Si heterostructure in the fields of thermoelectric and electronic applications, SiGe/Si heterostructures have been extensively investigated. For practical applications, thermal stability of the heterostructure during the thermoelectric power generation or fabrication process of electronic devices is of great concern. In this work, we focused on the effect of thermal annealing on the defect configuration in the SiGe/Si heterostructure. The formation mechanism of planar defects in an annealed SiGe/Si heterostructure was investigated by transmission electron microscopy. Due to the interdiffusion of Si and Ge, interface migration phenomena were observed in annealed heterostructures. Because of the strain gradient in the migrated region between the original interface and the migrated interface, the glide of misfit dislocation was observed in the region and planar defects were produced by the interaction of the gliding misfit dislocations. The planar defects were confined to the migrated region, and dislocation pileup by strain gradient was the origin of the confinement of the planar defect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.8
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• pp.661-665
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• 2007

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence $(<200^{\circ}C)$ on electrical properties. The feasible application in $1{\sim}2GHz$ frequency from measured data $BV_{CEO}{\sim}10V,\;f_T{\sim}14GHz,\;{\beta}{\simeq}110,\;NF{\sim}1dB$ using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

• ETRI Journal
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• v.41 no.6
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• pp.829-837
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• 2019

The p-type nanowire field-effect transistor (FET) with a SiGe shell channel on a Si core is optimally designed and characterized using in-depth technology computer-aided design (TCAD) with quantum models for sub-10-nm advanced logic technology. SiGe is adopted as the material for the ultrathin shell channel owing to its two primary merits of high hole mobility and strong Si compatibility. The SiGe shell can effectively confine the hole because of the large valence-band offset (VBO) between the Si core and the SiGe channel arranged in the radial direction. The proposed device is optimized in terms of the Ge shell channel thickness, Ge fraction in the SiGe channel, and the channel length (L_g) by examining a set of primary DC and AC parameters. The cutoff frequency (f_T) and maximum oscillation frequency (f_max) of the proposed device were determined to be 440.0 and 753.9 GHz when L_g is 5 nm, respectively, with an intrinsic delay time (τ) of 3.14 ps. The proposed SiGe-shell channel p-type nanowire FET has demonstrated a strong potential for low-power and high-speed applications in 10-nm-and-beyond complementary metal-oxide-semiconductor (CMOS) technology.

• 한국전자현미경학회:학술대회논문집
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• 1995.12a
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• pp.21-24
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• 1995

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.12-17
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• 2011

In this work, the analog performances of n-MOSFET fabricated on strained-Si/relaxed Si buffer layer with Ge mole fractions and thermal annealing temperatures after device fabrication have been characterized in Depth. The effective electron mobility was increased with the increase of Ge mole fraction for all annealing temperatures. However the effective electron mobility was decreased at the Ge mole fraction of 32%. The analog performances were enhanced with the increase of Ge mole fraction at the room temperature but they were degraded at the Ge mole fraction of 32%. Since the degradation of the effective electron mobility of strained-Si layer is more significant than one of conventional Si layer at elevated temperature, the degradation of analog performances of SGOI devices were increased than those of SOI devices.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.415-419
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• 2014

나노스케일 MOSFET에서 leakage current는 중요한 이슈로서 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current에 어떤 영향을 미칠 것인지 시뮬레이션을 통하여 알아보았다. $Si_{1-x}Ge_x$ alloy에서 Ge의 비율이 증가할수록 유효질량이 작아졌으나 conduction band minimum의 위치는 Si에 비해 상승하였다. 이로 인해 tunneling 확률이 증가하여 $Si_{1-x}Ge_x$ alloy를 substrate로 사용할 경우 leakage current를 더욱 증가시키게 되었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.876-884
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• 2017

The current-voltage characteristics of Silicon(Si), Germanum(Ge), and hetero tunnel field-effect transistors(TFETs) with source-overlapped gate structure was investigated using TCAD simulations in terms of tunneling. A Si-TFET with gate oxide material $SiO_2$ showed the hump effects in which line and point tunneling appear simultaneously, but one with gate oxide material $HfO_2$ showed only the line tunneling due to decreasing threshold voltage and it shows better performance than one with gate oxide material $SiO_2$. Tunneling mechanism of Ge and hetero-TFETs with gate oxide material of both $SiO_2$ and $HfO_2$ are dominated by point tunneling, and showed higher leakage currents, and Si-TFET shows better performance than Ge and hetero-TFETs in terms of SS. These simulation results of Si, Ge, and hetero-TFETs with source-overlapped gate structure can give the guideline for optimal TFET structures with non-silicon channel materials.

• Proceedings of the Materials Research Society of Korea Conference
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• 1994.11a
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• pp.39-39
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• 1994