• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.519-522
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• 2002

In this paper, we analyze the impact of plasma etching process induced device degradation on low temperature poly-Si TFTs. The results indicate the relationship between device degradation and PPID effect during plasma fabrication. The dual-gate structure, which is used to suppress leakage current, is also discussed in this research.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.3
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• pp.449-455
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• 1997

The anisotropic etching behavior of single crystal silicon were studied in aqueous KOH solution. N-type (100) oriented single crystal silicon wafers were used for the study, and the $SiO_2$ layer, whose etching rate is known to be much slower than that of silicon in the KOH solution, was used as a mask for the silicon etching. The silicon etching rate and the etching properties are shown to be a function of etchant temperature uniformity, circulation speed, and circulation direction of the etchant as well as the etchant concentration and the temperature. The etching rate is increased as the temperature is increased from $10\mu \textrm{m}/hr$ to $250\mu \textrm{m}/hr$ in the range of $50^{\circ}C~105^{\circ}C$. Hillock density and height is observed to be correlated with the etchant concentration and the etch temperature. The variation of the hillock density was explained by the ratio between the etching rate of (100) orientation and that of (111) orientation.

• Korean Journal of Metals and Materials
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• v.47 no.11
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• pp.748-753
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• 2009

The surface morphology and the surface roughness of n-type SiC induced by wet-treatment using 45% KOH and buffered oxide etchant (BOE-1HF : $6H_2O$) were investigated by atomic force microscopy (AFM). While Si-face of SiC could be etched by alkali solutions such as KOH, acidic solutions such as BOE were hardly able to etch SiC. When the rough SiC samples were used, the surface roughness of etched sample was decreased after wet-treatment regardless of etchant, due to the planarization the of surface by widening of scratches formed by mechanical polishing. It was observed that the initial etching was affected by the energetically unstable sites, such as dangling bond and steps. However, when a relatively smooth sample was used, the surface roughness was rapidly increased after treatment at $180^{\circ}C$ for 1 hr and at room temperature for 4 hr by using KOH solution, resulting from the nano-sized structures such as pores and bumps. This indicates that porous SiC surface can be achieved by using purely chemical treatment.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.23-29
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• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Korean Journal of Materials Research
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• v.20 no.11
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• pp.617-622
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• 2010

We have studied methods to save Si source during the fabrication process of crystalline Si solar cells. One way is to use a thin silicon wafer substrate. As the thickness of the wafers is reduced, mechanical fractures of the substrate increase with the mechanical handling of the thin wafers. It is expected that the mechanical fractures lead to a dropping of yield in the solar cell process. In this study, the mechanical properties of 220-micrometer-solar grade Cz p-type monocrystalline Si wafers were investigated by varying saw-damage etching conditions in order to improve the flexural strength of ultra-thin monocrystalline Si solar cells. Potassium hydroxide (KOH) solution and tetramethyl ammonium hydroxide (TMAH) solution were used as etching solutions. Etching processes were operated with a varying of the ratio of KOH and TMAH solutions in different temperature conditions. After saw-damage etching, wafers were cleaned with a modified RCA cleaning method for ten minutes. Each sample was divided into 42 pieces using an automatic dicing saw machine. The surface morphologies were investigated by scanning electron microscopy and 3D optical microscopy. The thickness distribution was measured by micrometer. The strength distribution was measured with a 4-point-bending tester. As a result, TMAH solution at $90^{\circ}C$ showed the best performance for flexural strength.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.1-5
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• 2009

This investigation is applied Taguchi method and the analysis of variance(ANOVA) to the reactive ion etching(RIE) characteristics of $SiO_2$ film coated on a wafer with Experimental Analysis and Optimization of $CF_4/O_2$ Plasma Etching Process mixture. Plans of experiments via nine experimental runs are based on the orthogonal arrays. A $L_9$ orthogonal array was selected with factors and three levels. The three factors included etching time, RF power, gas mixture ratio. The etching rate of the film were measured as a function of those factors. In this study, the etching thickness mean and uniformity of thickness of the RIE are adopted as the quality targets of the RIE etching process. The partial factorial design of the Taguchi method provides an economical and systematic method for determining the applicable process parameters. The RIE are found to be the most significant factors in both the thickness mean and the uniformity of thickness for a RIE etching process.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.39-45
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• 2012

Three-dimensional integrated circuit(3D IC) technology has become increasingly important due to the demand for high system performance and functionality. In this work, BOE and HF wet etching of Cu line surfaces after CMP were conducted for Cu-Cu pattern direct bonding. Step height of Cu and $SiO_2$ as well as Cu dishing after Cu CMP were analyzed by the 3D-Profiler. Step height increased and Cu dishing decreased with increasing BOE and HF wet etching times. XPS analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE and HF wet etching treatment. BOE treatment showed not only the effective $SiO_2$ etching but also reduced dishing and Cu surface oxide rather than HF treatment, which can be used as an meaningful process data for reliable Cu-Cu pattern bonding characteristics.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.88.1-88.1
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• 2012

Silicon nanowires (SiNWs), due to their unusual quantum-confinement effects that lead to superior electrical and optical properties compared to those of the bulk silicon, have been widely researched as a potential building block in a variety of novel electronic devices. The conventional means for the synthesis of SiNWs has been the vapor-liquid-solid method using chemical vapor deposition; however, this method is time consuming, environmentally unfriendly, and do not support vertical growth. As an alternate, the electroless etching method has been proposed, which uses metal catalysts contained in aqueous hydrofluoric acids (HF) for vertically etching the bulk silicon substrate. This new method can support large-area growth in a short time, and vertically aligned SiNWs with high aspect ratio can be readily synthesized with excellent reproducibility. Nonetheless, there still are rooms for improvement such as the poor surface characteristics that lead to degradation in electrical performance, and non-uniformity of the diameter and shapes of the synthesized SiNWs. Here, we report a facile method of SiNWs synthesis having uniform sizes, diameters, and shapes, which may be other than just cylindrical shapes using a modified nanosphere lithography technique. The diameters of the polystyrene nanospheres can be adjustable through varying the time of O2 plasma treatment, which serve as a mask template for metal deposition on a silicon substrate. After the removal of the nanospheres, SiNWs having the exact same shape as the mask are synthesized using wet etching technique in a solution of HF, hydrogen peroxide, and deionized water. Different electrical and optical characteristics were obtained according to the shapes and sizes of the SiNWs, which implies that they can serve specific purposes according to their types.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.53.2-53.2
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• 2010

In this study, we focused on our specialized electrode process for Si back-contact crystalline solar cell. It is different from other well-known back-contact cell process for thermal aspect and specialized process. In general, aluminum makes ohmic contact to the Si wafer and acts as a back surface reflector. And, silver is used for low series resistance metal grid lines. Aluminum was sputtered onto back side of wafer. Next, silver is directly patterned on the wafer by screen printing. The sputtered aluminum was removed by wet etching process after rear silver electrode was formed. In this process, the silver paste must have good printability, electrical property and adhesion strength, before and after the aluminum etching process. Silver paste also needs low temperature firing characteristics to reduce the thermal budget. So it was seriously collected by the products of several company of regarding low temperature firing (below $250^{\circ}C$) and aluminum etching endurance. First of all, silver pastes for etching selectivity were selected to evaluate as low temperature firing condition, electrical properties and adhesive strength. Using the nano- and micron-sized silver paste, so called hybrid type, made low temperature firing. So we could minimize the thermal budget in metallization process. Also the adhesion property greatly depended on the composition of paste, especially added resin and inorganic additives. In this paper, we will show that the metallization process of back-contact solar cell was realized as optimized nano-paste characteristics.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.30-34
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• 2019

We analyzed how the features in plasma information based virtual metrology (PI-VM) for SiO₂ etching depth with variation of 5% contribute to the prediction accuracy, which is previously developed by Jang. As a single feature, the explanatory power to the process results is in the order of plasma information about electron energy distribution function (PI_EEDF), equipment, and optical emission spectroscopy (OES) features. In the procedure of stepwise variable selection (SVS), OES features are selected after PI_EEDF. Informative vector for developed PI-VM also shows relatively high correlation between OES features and etching depth. This is because the reaction rate of each chemical species that governs the etching depth can be sensitively monitored when OES features are used with PI_EEDF. Securing PI_EEDF is important for the development of virtual metrology (VM) for prediction of process results. The role of PI_EEDF as an independent feature and the ability to monitor variation of plasma thermal state can make other features in the procedure of SVS more sensitive to the process results. It is expected that fault detection and classification (FDC) can be effectively developed by using the PI-VM.