• Korean Journal of Crystallography
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• v.9 no.1
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• pp.53-63
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• 1998

The Cd1-xZnxS thin films were grown on the Si(100) wafers by a hot wall epitaxy method (HWE). the source and substrate temperature are 600℃ and 440℃, respectively. The crystalline structure of epilayers was investigated by double crystal X-ray diffraction (DCXD). Hall effect on the sample was measured by the van der Pauw method and the carrier density and mobility dependence of Hall characteristics on temperature was also studied. In order to explore the applicability as a photoconductive cell, we measured the sensitivity (γ), the ratio of photocurrent to darkcurrent (pc/dc), maximum allowable power dissipation (MAPD), spectral response and response time. The results indicated that the best photoconductive characteristic were observed in the Cd0.53Zn0.47S samples annealed in Cu vapor comparing with in Cd, Se, air and vacuum vapour. Then we obtained the sensitivity of 0.99, the value of pc/dc of 1.65 × 107, the MAPD of 338mW, and the rise and decay time of 9.7 ms and 9.3 ms, respectively.

• Electrical & Electronic Materials
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• v.10 no.7
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• pp.692-699
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• 1997

The silicon doped $Al_{0.33}$G $a_{0.67}$As were grown by molecular beam epitaxy. The electroreflectance(ER) spectra of Schottky barrier Au/n-Al/suu x/G $a_{1-x}$ As have been measured at various modulation voltage( $V_{ac}$ ) and dc bias voltage( $V_{bias}$). From the observed Franz-Keldysh oscillations(FKO) peak, the band gap energy of the $Al_{x}$G $a_{1-x}$ As is 1.91 eV which corresponds to an Al composition of 33%. The internal electric field( $E_{i}$)of this sample is 2.96$\times$10$^{5}$ V/cm. As the modulation voltage( $V_{ac}$ ) is changed, the line shape of ER signal does not change but its amplitude varies linearly. The amplitude as a function of modulation voltage has saturated at 0.8 V. The internal electric field has decreased from 6.47$\times$10$^{5}$ V/cm to 2.00$\times$10$^{5}$ V/cm as the dc bias voltage( $V_{bias}$) increases from -3.5 V to +0.8 V. The values of built-in voltage( $V_{bi}$ ) and carrier concentration(N) determined from the plot of $V_{bias}$ from the plot of $V_{bias}$ versus $E_{i}$$^{2}$ are 0.855 V and 3.83$\times$10$^{17}$ c $m^{-3}$ , respectively.ively.y.y.y.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.1
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• pp.1-5
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• 2009

In this study, we performed growth of InGaN/GaN multi quantum well (MQW) structures on semi-polar (1-10]) GaN facet on 8-degree off oriented stripe patterned (100) Si substratcs by MOVPE. The structural and optical properties of the InGaN/GaN multi quantum well (MQW) structures grown on (1-101) GaN stripe depend on $NH_3$ flow rate, TMI flow rate and growth temperature are characterized by cathodoluminescence (CL) and scanning electron microscopy (SEM). With the decrease of $NH_3$ flow rate, the threading dislocation of (1-101) GaN is considerably reduced. We could control the transition wavelength of InGaN/GaN MQW structures from 391.5 nm to 541.2 nm depend on the growth conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.4
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• pp.285-296
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• 2005

Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 ％ in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.

• Applied Chemistry for Engineering
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• v.10 no.3
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• pp.354-361
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• 1999

The films annealed after physical deposition of titanium and chemical deposition of amorphous silicon by plasma were formed Si-rich titanium silicide with a good quality of crystallinity and had the various lattice structures due to orientation of lattices for epitaxy growth during annealing process. Band gap of the titanium silicide had 1.14~1.165 eV and the films annealed after chemical deposition of a-Si:H by plasma were influenced by a-Si and the dangling bond offered by desorption of hydrogen. Urbach tail ($E_0$) of the films annealed after physical deposition of Ti was nearly constant within a range of 0.045~0.05 eV, and the number of defect in films annealed after chemical deposition of a-Si:H by plasma was about 2~3 times more than that in annealed Ti/Si films.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.289-289
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• 2012

Molecular beam epitaxy 방법으로 성장시킨 AlGaAs/GaAs 다중 양자 우물 구조에 대한 라만 산란 연구를 보고한다. InAs 양자점이 성장된 Si 기판 위에 각기 다른 온도에서 두께 약 1 ${\mu}m$의 GaAs 층을 두 단계로 성장시킨 후 그 위에 AlGaAs/GaAs 다중 양자 우물 구조를 성장시켰다. AlGaAs/GaAs 다중 양자 우물 구조의 광학적 특성에 영향을 주는 GaAs 층의 변형력(stress)의 변화를 알기 위해서 시료의 측면으로부터 공간 분해된 라만 산란 실험을 수행하였다. 라만 산란 실험으로부터 AlGaAs/GaAs 다중 양자 우물 구조가 지니는 모든 종류의 광학 포논을 관측하였으며, 두 단계로 성장시킨 GaAs 층에서의 변형력이 Si 기판으로부터 멀어질수록 성장조건의 변화에 따라서 다르게 전개된다는 것을 파악하였다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.79-79
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• 2003

최근 CMOS(Complementary Metal Oxide Semiconductor) 능동소자에 사용되는 MOS-FET (Metal Oxide Semiconductror Field Effect Transitror)의 전체적인 크기 감소추세에 따라 금속 전극과 반도체 사이의 절연층 두께 감소가 요구되고 있다. 현재 보편적으로 사용되고 있는 SiO$_2$층은 두께 감소에 따른 터널링 전류의 증가로 더 이상의 두께 감소를 기대하기 어려운 상태이다. 이러한 배경에서 최근 터널링 전류를 충분히 감소시키면서 요구되는 절연특성을 얻을 수 있는 새로운 고유전 물질 (high-k dielectric material)에 대한 연구가 이루어지고 있다. 현재까지 연구되어온 고유전 물질 중, 고유전 상수, 큰 밴드갭, Si과의 열적 안정성을 갖는 물질로 ZrO$_2$가 주목을 받고 있다. 본 연구에서는 Metal Organic Molecular Beam Epitaxy (MOMBE) 방법을 이용한 ZrO$_2$ 층의 성장조건 및 특성을 평가하고자 한다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.37-37
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• 2003

Ferroelectric random acess memories (FeRAMs) 재료로 주목받고 있는 강유전 물질은 이미 여러 해 전부터 많은 물질들에 대해 연구가 진행되어 왔다. 그 중 낮은 공정 온도를 가지며 큰 remanent polarization 값을 갖는 lead zirconium titanate (PZT) 박막에 대해 많은 연구가 진행되고 있다. 하지만 Pt 기판위에 증착된 PZT 박막은 높은 피로 현상을 보이는 문제가 있다. 최근 Pulsed laser deposition이나 metal-organic vapor phase epitaxy (MOVPE) 등의 방법에 의해 epitaxial substituted-$Bi_4Ti_3O_{12}$ (La, Nd) 박막에 대해 보고가 되고 있다. 본 연구에서는 높은 remanent polarization 값을 갖는 $(Bi,Ce)_4Ti_3O_{12}$ (BCT) 박막을 pulsed laser deposition 방법을 사용하여 증착하였다. 또한 Bismuth의 양을 변화시켜 Bismuth의 양에 따른 remanent polarization의 변화를 확인하여 보았다. 사용된 기판은 Pt/$TiO_2$/$SiO_2$/Si 기판을 사용하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.54-58
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• 1994

H$_2$ bake and GeH$_4$ clean are used as a in-situ pre-clean method in low temperature Si based epitaxial growth technology using rapid thermal processing chemical vapor deposition (RTPCVD). In this paper, the H$_2$ bake and GeH$_4$ clean processes are optimized for low surface defect density using Taguchi method. In H$_2$ bake process, the epitaxial growth temperature affects dominantly on the surface defect density, and the next affecting factors are H$_2$ bake temperature and rinse time in de-ionised water. In GeH$_4$ clean process, GeH$_4$ clean temperature affects most strongly on the surface defect density, and the minor factor is GeH$_4$flow rate. The optimum process conditions predicted fly Taguchi method agree well with tile experimental data in both in-situ clean processes.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.460-460
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• 2013

본 연구는 Si (111) 기판위에 Ga 분자선량을 변화시켜 GaN 박막을 molecular beam epitaxy 법으로 성장하고, Schottky 장벽 다이오드를 제작한 후에 deep level transient spectroscopy (DLTS) 법을 통하여 깊은 준위 결함에 대하여 조사하였다. 성장 시 Ga 분자선량은, 그리고 Torr로 달리하여 V/III 비율을 변화시켰고, Schottky 장벽 다이오드 제작을 위하여 e-beam evaporator를 사용하여 metal을 증착하였다. Schottky 접촉에는 Ni (20 nm)/Au (100 nm)를 증착하였고, ohmic 접촉에는 Ti (20 nm)/Au (100 nm)를 증착하고 I-V, C-V 그리고 DLTS를 측정하였다. DLTS 신호를 통해 GaN 박막 성장 과정에서 형성되는 깊은 결함의 종류를 확인하였으며, 열처리 등의 처리 및 측정 조건변화에 따른 결함의 거동과 종류 및 원인에 대하여 분석 설명하였다.