• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.31-36
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• 2015

The demand for multi-functionality, high density, high performance, and miniaturization of IC devices has caused the technology paradigm shift for electronic packaging. So, thermal management of new packaged chips becomes a bottleneck for the performance of next generation devices. Among various thermal solutions such as heat sink, heat spreader, TIM, thermoelectric cooler, etc. on-chip liquid cooling module was investigated in this study. Micro-channel was fabricated on Si wafer using a deep reactive ion etching, and 3 different micro-channel designs (straight MC, serpentine MC, zigzag MC) were formed to evalute the effectiveness of liquid cooling. At the heating temperature of $200^{\circ}C$ and coolant flow rate of 150ml/min, straight MC showed the high temperature differential of ${\sim}44^{\circ}C$ after liquid cooling. The shape of liquid flowing through micro-channel was observed by fluorescence microscope, and the temperarue differential of liquid cooling module was measuremd by IR microscope.

• Journal of Sensor Science and Technology
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• v.22 no.2
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.