• 한국전기전자재료학회논문지
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• 제15권11호
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• 마이크로전자및패키징학회지
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• 제14권2호
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• pp.17-21
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• 2007

밀도가 높고 주기적으로 배열된 실리콘 나노점이 실리콘 기판위에 형성 되었다. 실리콘 나노점을 형성하기 위해 사용된 나노패턴의 지름은 $15{\sim}40$ 나노미터(nm)이고 깊이는 40 nm 이었으며 기공과 기공 사이의 거리는 $40{\sim}80\;nm$ 이었다. 나노미터 크기의 패턴을 형성시키기 위해서 자기조립물질을 사용했으며 폴리스티렌(PS) 바탕에 벌집형태로 평행하게 배열된 실린더 모양의 폴리메틸메타아크릴레이트(PMMA)의 구조를 형성하였다. 폴리메틸메타아크릴레이트를 아세트산으로 제거하여 폴리스티렌만 남아있는 나노크기의 마스크를 만들었다. 형성된 나노패턴에 전자빔 기상증착장치를 사용하여 금 박막을 $100\;{\AA}$ 증착하고 리프트오프(lift-off) 방식으로 금 나노점을 만들었다. 형성된 금 나노점을 불소기반의 화학반응성 식각법을 이용하여 식각하고 황산으로 제거하였다. 형성된 실리콘 나노점의 지름은 $30{\sim}70\;nm$였고 높이는 $10{\sim}20\;nm$ 였다.

• Applied Microscopy
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• 제50권
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• pp.17.1-17.9
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• 2020

Recent advances in fabrication have enabled radial-junction architectures for cost-effective and high-performance optoelectronic devices. Unlike a planar PN junction, a radial-junction geometry maximizes the optical interaction in the three-dimensional (3D) structures, while effectively extracting the generated carriers via the conformal PN junction. In this paper, we report characterizations of radial PN junctions that consist of p-type Si micropillars created by deep reactive-ion etching (DRIE) and an n-type layer formed by phosphorus gas diffusion. We use electron-beam induced current (EBIC) microscopy to access the 3D junction profile from the sidewall of the pillars. Our EBIC images reveal uniform PN junctions conformally constructed on the 3D pillar array. Based on Monte-Carlo simulations and EBIC modeling, we estimate local carrier separation/collection efficiency that reflects the quality of the PN junction. We find the EBIC efficiency of the pillar array increases with the incident electron beam energy, consistent with the EBIC behaviors observed in a high-quality planar PN junction. The magnitude of the EBIC efficiency of our pillar array is about 70% at 10 kV, slightly lower than that of the planar device (≈ 81%). We suggest that this reduction could be attributed to the unpassivated pillar surface and the unintended recombination centers in the pillar cores introduced during the DRIE processes. Our results support that the depth-dependent EBIC approach is ideally suitable for evaluating PN junctions formed on micro/nanostructured semiconductors with various geometry.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권4호
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• pp.259-267
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• 2002

We present a novel 3D fabrication method with single X-ray process utilizing an X-ray mask in which a micro-actuator is integrated. An X-ray absorber is electroplated on the shuttle mass driven by the integrated micro-actuator during deep X-ray exposures. 3D microstructures are revealed by development kinetics and modulated in-depth dose distribution in resist, usually PMMA. Fabrication of X-ray masks with integrated electrothermal xy-stage and electrostatic actuator is presented along with discussions on PMMA development characteristics. Both devices use $20-\mu\textrm{m}$-thick overhanging single crystal Si as a structural material and fabricated using deep reactive ion etching of silicon-on-insulator wafer, phosphorous diffusion, gold electroplating, and bulk micromachining process. In electrostatic devices, $10-\mu\textrm{m}-thick$ gold absorber on $1mm{\times}1mm$ Si shuttle mass is supported by $10-\mu\textrm{m}-wide$, 1-mm-long suspension beams and oscillated by comb electrodes during X-ray exposures. In electrothermal devices, gold absorber on 1.42 mm diameter shuttle mass is oscillated in x and y directions sequentially by thermal expansion caused by joule heating of the corresponding bent beam actuators. The fundamental frequency and amplitude of the electrostatic devices are around 3.6 kHz and $20\mu\textrm{m}$, respectively, for a dc bias of 100 V and an ac bias of 20 VP-P (peak-peak). Displacements in x and y directions of the electrothermal devices are both around $20{\;}\mu\textrm{m}$at 742 mW input power. S-shaped and conical shaped PMMA microstructures are demonstrated through X-ray experiments with the fabricated devices.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.389-390
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• 2012

In this study, we fabricate a superhydrophobic surface made of hierarchical nanostructures that combine wax crystalline structure with moth-eye structure using vacuum cluster system and measure their hydrophobicity and durability. Since the lotus effect was found, much work has been done on studying self-cleaning surface for decades. The surface of lotus leaf consists of multi-level layers of micro scale papillose epidermal cells and epicuticular wax crystalloids [1]. This hierarchical structure has superhydrophobic property because the sufficiently rough surface allows air pockets to form easily below the liquid, the so-called Cassie state, so that the relatively small area of water/solid interface makes the energetic cost associated with corresponding water/air interfaces smaller than the energy gained [2]. Various nanostructures have been reported for fabricating the self-cleaning surface but in general, they have the problem of low durability. More than two nanostructures on a surface can be integrated together to increase hydrophobicity and durability of the surface as in the lotus leaf [3,5]. As one of the bio-inspired nanostructures, we introduce a hierarchical nanostructure fabricated with a high vacuum cluster system. A hierarchical nanostructure is a combination of moth-eye structure with an average pitch of 300 nm and height of 700 nm, and the wax crystalline structure with an average width and height of 200 nm. The moth-eye structure is fabricated with deep reactive ion etching (DRIE) process. $SiO_2$ layer is initially deposited on a glass substrate using PECVD in the cluster system. Then, Au seed layer is deposited for a few second using DC sputtering process to provide stochastic mask for etching the underlying $SiO_2$ layer with ICP-RIE so that moth-eye structure can be fabricated. Additionally, n-hexatriacontane paraffin wax ($C_{36}H_{74}$) is deposited on the moth-eye structure in a thermal evaporator and self-recrystallized at $40^{\circ}C$ for 4h [4]. All of steps are conducted utilizing vacuum cluster system to minimize the contamination. The water contact angles are measured by tensiometer. The morphology of the surface is characterized using SEM and AFM and the reflectance is measured by spectrophotometer.

• Journal of Welding and Joining
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• 제24권2호
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• 대한금속재료학회지
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• 제50권2호
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• 마이크로전자및패키징학회지
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• 제22권2호
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• pp.27-31
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• 2015

고성능 소자의 전력밀도가 증가함에 따라 소자의 열 관리는 주요 핵심 기술로 부각되었고, 기존의 heat sink나 TIM(thermal interface material)으로는 소자의 열 문제를 해결하는데 한계가 있다. 이에 최근에는 열 유속(heat flux)을 증가시키고자 액체 냉각 시스템에 관한 연구가 활발히 진행되고 있으며, 본 연구에서는 TSV(through Si via)와 microchannel을 이용하여 칩 레벨 액체 냉각 시스템을 제작하고 시스템의 냉각 특성을 분석하였다. TSV와 microchannel은 Si 웨이퍼에 DRIE(deep reactive ion etching)을 이용하여 공정하였고, 3가지 다른 형상의 TSV를 제작하여 TSV 형상이 냉각 효율에 미치는 영향을 분석하였다. TSV와 microchannel 내 액체흐름 형상은 형광현미경으로 관찰하였고, 액체 냉각에 대한 효율은 실온에서 $300^{\circ}C$까지 시편을 가열하면서 적외선현미경을 이용하여 온도를 측정 분석하였다.

• 대한금속재료학회지
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• 제48권7호
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.