• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.407-407
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• 2014

Nanotechnology, especially vertically grown silicon nanowires, has gotten great attentions in biology due to characteristics of one dimensional nanostructure; controllable synthetic structure such as lengths, diameters, densities. Silicon nanowires are promising materials as nanoelectrodes due to their highly complementary metal-oxide-semiconductor (CMOS) - and bio-compatibility. Silicon nanowires are so intoxicated that are effective for bio molecular delivery and electrical stimulation. Vertical nanowires with integrated Au tips were fabricated for electrical intracellular interfacing with PC-12 cells. We have made synthesized two types of nanowire devices; one is multi-nanowires electrode for bio molecular sensing and electrical stimulation, and the other is single-nanowires electrode respectively. Here, we demonstrate that differentiation of Nerve Growth Factor (NGF) treated PC-12 cells can be promoted depending on different magnitudes of electrical stimulation and density of Si NWs. It was fabricated by both bottom-up and top-down approaches using low pressure chemical vapor deposition (LPCVD) with high vacuuming environment to electrically stimulate PC-12 cells. The effects of electrical stimulation with NGF on the morphological differentiation are observed by Scanning Electron Microscopy (SEM), and it induces neural outgrowth. Moreover, the cell cytosol can be dyed selectively depending on the degree of differentiation along with fluorescence microscopy measurement. Vertically grown silicon nanowires have further expected advantages in case of single nanowire fabrication, and will be able to expand its characteristics to diverse applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.152-152
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• 2011

Silicon 기반의 환경에서 연구 및 제조되는 전자소자는 반도체의 기술이 발전함에 따라 chip 선폭의 크기가 30 nm에서 20 nm, 그리고 그 이하의 크기로 점점 더 작아지는 요구에 직면하고 있다. 탄소나노 구조와 나노와이어 기술이 Silicon을 대신할 다음세대 기술로 주목받고 있다. 많은 연구결과들 중에서 III-V CMOS가 가장 빠른 접근 방법이라 예상한다. III-V족 물질을 이용하면 electron 보다 수십 배 이상의 이동도를 얻을 수 있으나 p-type의 구조를 구현하는 것이 해결해야 할 문제이다. p-type 3-5 족 화합물을 이용하여 에너지 밴드 갭의 변화를 가능하게 한다면 hole의 이동도를 크게 향상시킬 수 있어 silicon 기반의 p-type 소자보다 2~3배 더 빠른 소자의 구현이 가능하다. 3-5족 화합물 반도체의 성장 기술이 많이 진보되어 이를 이용하여 고속 소자를 구현한다면 시기적으로 더욱 빨리 다가올 것이라 예측한다. 에너지 밴드갭의 변화와 격자 부정합을 고려하여 SI InP 기판에 GaSb 물질을 채널로 사용한 p-type 2-dimensional hole gas (2DHG) 소자를 구현하였다. 관찰된 소자 구조의 박막 상태의 특징을 보이며 10 um ${\times}$ 10 um AFM 측정결과 1 nm 이하의 표면 거칠기를 가지며 상온에서의 hole 이동도는 약 650 cm2/Vs이고 sheet carrier density는 $5{\times}1012$ /cm2의 결과를 확인하였다. 실험결과 InP 기판위에 채널로 사용된 GaSb 박막을 올리는데 있어 가장 중요한 것은 Phosphorus, Arsenic, 그리고 Antimony 물질의 양과 이들의 변화시간의 조절이다. 본 발표에서 Semi-insulating InP 기판위에 electron이 아닌 hole을 반송자로 이용한 차세대 고속 전자소자를 구현하고자 하여 MBE (Molecular Beam Epitaxy)로 p-type 소자를 구현하여 실험하였다. 아울러 더욱 빠른 소자의 구현을 위하여 세계의 유수 그룹들의 연구 결과들과 앞으로 예상되는 고속 소자에 대해서 비교와 함께 많은 기술에 대해 논의하고자 한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.284-284
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• 2011

Ion sensitive field effect transistor (ISFET)는 용액 중의 각종 이온 농도를 측정하는 반도체 이온 센서이다. ISFET는 작은 소자 크기, 견고한 구조, 즉각적인 반응속도, 기존의 CMOS공정과 호환이 가능하다는 장점이 있다. ISFET의 기본 구조는 기존의 metal oxide semiconductor field effect transistor (MOSFET)에서 고안되었으며, ISFET는 기존의 MOSFET의 게이트 전극 부분이 기준전극과 전해질로 대체되어진 구조를 가지고 있다. ISFET소자의 pH 감지 메커니즘은 감지막의 표면에서 pH용액의 수소이온이 막의 표면에 속박되어 표면전위의 변화를 유발하는 것에 기인한다. 그 결과, 수소이온의 농도에 따라 ISFET의 문턱전압의 변화를 일으키게 되고 드레인 전류의 양 또한 달라지게 된다. 한편, ISFET의 좋은 pH감지특성과 높은 출력특성을 얻기 위하여 high-k물질들이 감지막으로써 지속적으로 연구되어져 왔다. 그 중 Al2O3와 HfO2는 높은 유전상수와 좋은 pH 감지능력으로 인하여 많은 연구가 이루어져온 물질이다. 하지만 HfO2는 높은 유전상수를 갖음에도 불구하고 화학용액에 대한 non-ideal 효과에 취약하다는 보고가 있다. 반면에 Al2O3의 유전상수는 HfO2보다 작지만 화학용액으로 인한 손상에 대하여 강한 immunity가 있는 재료이다. 본 연구에서는, 이러한 각각의 high-k 물질들의 단점을 보안하기 위하여 SiO2/HfO2/Al2O3(OHA) 적층막을 이용한 ISFET pH 센서를 제작하였으며 SOI 기판에서 구현되었다. SOI기판에서 OHA 적층막을 이용한 ISFET 제작이 이루어짐에 따라서 소자의 signal to noise 비율을 증대 시킬것으로 기대된다. 실제로 SOI-ISFET와 같이 제작된 SOI-MOSFET는 1.8${\times}$1010의 높은 on/off 전류 비율을을 보였으며 65 mV/dec의 subthreshold swing 값을 갖음으로써, 우수한 전기적 특성을 보이는 ISFET가 제작이 되었음을 확인 하였다. OHA 감지 적층막의 각 층은 양호한 계면상태, 높은 출력특성, 화학용액에 대한non-ideal 효과에 강한 immunity을 위하여 적층되었다. 결론적으로 SOI과 OHA 적층감지막을 이용하여 우수한 pH 감지 특성을 보이는 pH 센서가 제작되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• ETRI Journal
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• v.42 no.5
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• pp.781-789
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• 2020

In this study, an E-band low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) has been designed using silicon-germanium 130-nm bipolar complementary metal-oxide-semiconductor technology to suppress unwanted signal gain outside operating frequencies and improve the signal gain and noise figures at operating frequencies. The proposed impedance-controllable filter has series (R_s) and parallel (R_p) resistors instead of a conventional inductor-capacitor (L-C) filter without any resistor in an interstage matching circuit. Using the impedance-controllable filter instead of the conventional L-C filter, the unwanted high signal gains of the designed E-band LNA at frequencies of 54 GHz to 57 GHz are suppressed by 8 dB to 12 dB from 24 dB to 26 dB to 12 dB to 18 dB. The small-signal gain S₂₁ at the operating frequencies of 70 GHz to 95 GHz are only decreased by 1.4 dB to 2.4 dB from 21.6 dB to 25.4 dB to 19.2 dB to 24.0 dB. The fabricated E-band LNA MMIC with the proposed filter has a measured S₂₁ of 16 dB to 21 dB, input matching (S₁₁) of -14 dB to -5 dB, and output matching (S₂₂) of -19 dB to -4 dB at E-band operating frequencies of 70 GHz to 95 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.410-410
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• 2013

Next-generation nonvolatile memory (NVM) has attracted increasing attention about emerging NVMs such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory and resistance random access memory (RRAM). Previous studies have demonstrated that RRAM is promising because of its excellent properties, including simple structure, high speed and high density integration. Many research groups have reported a lot of metal oxides as resistive materials like TiO2, NiO, SrTiO3 and ZnO [1]. Among them, the ZnO-based film is one of the most promising materials for RRAM because of its good switching characteristics, reliability and high transparency [2]. However, in many studies about ZnO-based RRAMs, there was a problem to get lower current level for reducing the operating power dissipation and improving the device reliability such an endurance and an retention time of memory devices. Thus in this paper, we investigated that highly reproducible bipolar resistive switching characteristics of W doped ZnO RRAM device and it showed low resistive switching current level and large ON/OFF ratio. This may be caused by the interdiffusion of the W atoms in the ZnO film, whch serves as dopants, and leakage current would rise resulting in the lowering of current level [3]. In this work, a ZnO film and W doped ZnO film were fabricated on a Si substrate using RF magnetron sputtering from ZnO and W targets at room temperature with Ar gas ambient, and compared their current levels. Compared with the conventional ZnO-based RRAM, the W doped ZnO ReRAM device shows the reduction of reset current from ~$10^{-6}$ A to ~$10^{-9}$ A and large ON/OFF ratio of ~$10^3$ along with self-rectifying characteristic as shown in Fig. 1. In addition, we observed good endurance of $10^3$ times and retention time of $10^4$ s in the W doped ZnO ReRAM device. With this advantageous characteristics, W doped ZnO thin film device is a promising candidates for CMOS compatible and high-density RRAM devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.