• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권3호
• /
• pp.139-144
• /
• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Transactions on Electrical and Electronic Materials
• /
• 제18권6호
• /
• pp.341-344
• /
• 2017

Infrared (IR) filters were developed to implement integrated three-dimensional (3D) image sensors that are capable of obtaining both color image and depth information at the same time. The combination of light filters applicable to the 3D image sensor is composed of a modified IR cut filter mounted on the objective lens module and on-chip filters such as IR pass filters and color filters. The IR cut filters were fabricated by inorganic $SiO_2/TiO_2$ multilayered thin-film deposition using RF magnetron sputtering. On-chip IR pass filters were synthetized by dissolving various pigments and dyes in organic solvents and by subsequent patterning with photolithography. The fabrication process of the filters is fairly compatible with the complementary metal oxide semiconductor (CMOS) process. Thus, the IR cut filter and IR pass filter combined with conventional color filters are considered successfully applicable to 3D image sensors.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권3호
• /
• pp.367-374
• /
• 2016

This paper presents an electro-thermal modeling of an amorphous silicon (a-Si) uncooled microbolometer. This modeling provides a comprehensive solution for simulating the electro-thermal characteristics of the fabricated microbolometer and enables electro-thermal co-simulation between MEMS and CMOS integrated circuits. To validate this model, three types of uncooled microbolometers were fabricated using a post-CMOS surface micromachining process. The simulation results show a maximum discrepancy of 2.6% relative to the experimental results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권6호
• /
• pp.706-711
• /
• 2014

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제10권2호
• /
• pp.100-106
• /
• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2009년도 춘계학술발표대회
• /
• pp.22.1-22.1
• /
• 2009

차세대 CMOS 공정에서 유전상수가 높은 게이트 절연막과 함께 게이트 전극이 관심을 끌고 있다. 게이트 전극은 전도도가 높아야 하고 p-MOS, n-MOS에 맞는 일함수를 가져야 하며 열적 특성이 안정해야 한다. 탄탈룸 계열 탄화물이나 질화물은 게이트 전극으로 관심을 끌고 있는 물질이며 이를 원자층 화학증착법으로 박막화 하는 공정이 관심을 끌고 있다. 원자층 화학공정에서는 전구체의 역할이 중요하며 이의 기상반응 메카니즘, 표면 반응 메카니즘을 제대로 이해해야 한다. 본 연구에서는 TBTDET (tert-butylimido tris-diethylamido tantalum) 전구체의 반응 메커니즘을 FTIR(Fourier Transform Infrared)을 이용해 진단하였다. 또한 수소, 암모니아, 메탄을 이용한 열화학 원자층 증착, 플라즈마 원자층 증착 공정을 수행하여 박막을 얻고 이들의 특성을 평가하였다. 각 공정에 따라 반응 메커니즘이 달라지고 박막의 조성이 달라지며 또한 박막의 물성도 달라진다. 특히 박막에 형성되는 TaC, TaN, Ta3N5, Ta2O5 (증착 후 산소의 유입에 의해 형성됨) 등의 조성이 공정에 따라 달라지며 박막의 물성도 달라진다. 반응메카니즘의 연구를 통해 각 공정에서 어떠한 조성의 박막이 얻어지는 지를 규명하였고 박막의 밀도에 따라 산소유입량이 어떻게 달라지는 지를 규명하였다.

• Transactions on Electrical and Electronic Materials
• /
• 제3권3호
• /
• pp.14-17
• /
• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• 전자통신동향분석
• /
• 제33권6호
• /
• pp.34-40
• /
• 2018

Traditionally, many researchers have conducted research on terahertz technology utilizing optical devices such as lasers. However, nanometer-scale electronic devices using silicon or III-V compound semiconductors have received significant attention regarding the development of a terahertz system owing to the rapid scaling down of devices. This enables an operating frequency of up to approximately 0.5 THz for silicon, and approximately 1 THz for III-V devices. This article reviews the recent trends of terahertz monolithic integrated circuits based on several electronic devices such as CMOS, SiGe BiCMOS, and InP HBT/HEMT, and a particular quantum device, an RTD.

• 한국세라믹학회지
• /
• 제54권1호
• /
• pp.66-69
• /
• 2017

In this study, the fabrication and electrical properties of aligned single-walled carbon nanotube (SWCNT) networks using a template-based fluidic assembly process are presented. This complementary metal-oxide-semiconductor (CMOS)-friendly process allows the formation of highly aligned lateral nanotube networks on $SiO_2/Si$ substrates, which can be easily integrated onto existing Si-based structures. To measure outstanding electrical properties of organized SWCNT devices, interfacial contact resistance between organized SWCNT devices and Ti/Au electrodes needs to be improved since conventional lithographic cleaning procedures are insufficient for the complete removal of lithographic residues in SWCNT network devices. Using optimized purification steps and controlled developing time, the interfacial contact resistance between SWCNTs and contact electrodes of Ti/Au is reached below 2% of the overall resistance in two-probe SWCNT platform. This structure can withstand current densities ${\sim}10^7A{\cdot}cm^{-2}$, equivalent to copper at similar dimensions. Also failure current density improves with decreasing network width.

• Current Optics and Photonics
• /
• 제1권5호
• /
• pp.544-550
• /
• 2017

This simulation based study reports a novel tunable, compact, room temperature terahertz (THz) transistor source, operated on the concept of charge plasma oscillation with the capability of radiating within a terahertz gap. A vertical cavity with a quasi-periodic distributed-Bragg-reflector has been attached to a THz plasma wave transistor to achieve a monochromatic coherent surface emission for single as well as multi-color operation. The resonance frequency has been tuned from 0.5 to 1.5 THz with the variable quality factor of the optical cavity from 5 to 290 and slope efficiency maximized to 11. The proposed surface emitting terahertz transistor is able to satisfy the demand for compact solid state terahertz sources in the field of teratronics. The proposed device can be integrated with Si CMOS technology and has opened the way towards the development of silicon photonics.