• ETRI Journal
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• v.35 no.4
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• pp.730-733
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• 2013

In this work, buffer layers with various conditions are inserted at an n/i interface in hydrogenated amorphous silicon semitransparent solar cells. It is observed that the performance of a solar cell strongly depends on the arrangement and thickness of the buffer layer. When arranging buffer layers with various bandgaps in ascending order from the intrinsic layer to the n layer, a relatively high open circuit voltage and short circuit current are observed. In addition, the fill factors are improved, owing to an enhanced shunt resistance under every instance of the introduced n/i buffer layers. Among the various conditions during the arrangement of the buffer layers, a reverse V shape of the energy bandgap is found to be the most effective for high efficiency, which also exhibits intermediate transmittance among all samples. This is an inspiring result, enabling an independent control of the conversion efficiency and transmittance.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1041-1043
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• 2005

It is expected to reduce stresses to components of high voltage circuit breaker and transferred switching surge from power system by applying controlled switching technique to high voltage system. This technique has already been applied to switch shunt reactor or capacitor bank in advanced countries. In this paper, operating software is installed in developed controlled switching device and HMI(Human-machine Interface) is under developing, In the future, this technique is expected to contribute to S.A(Substation Automation).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.784-790
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• 2012

In this paper, an all-digital CMOS ultra-wideband(UWB) pulse generator for high band(6~10 GHz) frequency range is presented. The pulse generator is designed and implemented with extremely low power and low complexity. It is designed to meet the FCC spectral mask requirement by using Gaussian pulse shaping circuit and control the center frequency by using CMOS delay line with shunt capacitor. Measurement results show that the center frequency can be controlled from 4.5 GHz to 7.5 GHz and pulse width is 1.5 ns and pulse amplitude is 310 mV peak to peak at 10 MHz pulse repetition frequency(PRF). The circuit is implemented in 0.13 um CMOS process with a core area of only $182{\times}65um^2$ and dissipates the average power of 11.4 mW at an output buffer with 1.5-V supply voltage. However, the core consumes only 0.26 mW except for output buffer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1055-1063
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• 2013

Low noise amplifiers(LNAs) are an integral component of RF receivers and are frequently required to operate at wide frequency bands for various wireless systems. For wideband operation, important performance metrics such as voltage gain, return loss, noise figures and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high input matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor between gate and drain decreases the third-order harmonics at the output. Fabricated in $0.18{\mu}m$ CMOS process, the chip area of this LNA is $0.202mm^2$, including pads. Measurement results illustrate that input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 7~8 dB over 1.5~13 GHz. In addition, good linearity(IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

• ETRI Journal
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• v.35 no.3
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• pp.378-385
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• 2013

An S-band multifunction chip with a simple interface for an active phased array base station antenna for next-generation mobile communications is designed and fabricated using commercial 0.5-${\mu}m$ GaAs pHEMT technology. To reduce the cost of the module assembly and to reduce the number of chip interfaces for a compact transmit/receive module, a digital serial-to-parallel converter and an active bias circuit are integrated into the designed chip. The chip can be controlled and driven using only five interfaces. With 6-bit phase shifting and 6-bit attenuation, it provides a wideband performance employing a shunt-feedback technique for amplifiers. With a compact size of 16 $mm^2$ ($4mm{\times}4mm$), the proposed chip exhibits a gain of 26 dB, a P1dB of 12 dBm, and a noise figure of 3.5 dB over a wide frequency range of 1.8 GHz to 3.2 GHz.

• International Journal of Aeronautical and Space Sciences
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• v.15 no.1
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• pp.1-19
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• 2014

Attaching a piezoelectric transducer to a vibrating structure, and shunting it with an electric circuit, gives rise to different passive, semi-passive, and semi-active control techniques. This paper attempts to review the research related to structural vibration control, via passive, semi-passive, and semi-active control methods. First, the existing electromechanical modeling is reviewed, along with the modeling methods. These range from lumped parameters, to distributed parameters modeling of piezostructural systems shunted by electrical networks. Vibration control laws are then discussed, covering passive, semi-passive, and semi-active control techniques, which are classified according to whether external power is supplied to the piezoelectric transducers, or not. Emphasis is placed on recent articles covering semi-passive and semi-active control techniques, based upon switched shunt circuits. This review provides the necessary background material for researchers interested in the growing field of vibration damping and control, via shunted piezostructural systems.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.1058-1062
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• 2000

We investigated resistive superconducting fault current limites (SFCLs) fabricated using YBCO thin films on 2-inch diameter sapphire substrates. Nearly identical SFCL units were prepared and tested. The units were connected in series and parallel to increase the current and voltage ratings. A serial connection of the units showed significantly unbalanced power dissipation between the units. This imbalance was removed by introducing a shunt resistor to the firstly quenched unit. Parallel connection of the units increased the current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current 25 A$\_$peak/, was produced and successfully tested at a 220 V$\_$rms/circuit. From the resistance increase, we estimated that the film temperature increased to 200 K in 5 msec, and 300 K in 120 msec. Successive quenches revealed that this system is stable without degradation in the current limiting capability under such thermal shocks as quenches at 220 V$\_$rms/.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.10 s.101
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• pp.1003-1009
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• 2005

In this paper, small-size high-power single pole double throw(SPDT) switch with defected pound structure(DGS) is presented for wireless broadband internet application. To reduce the circuit size using slow-wave characteristic, the DGS is applied to ${\lambda}/4$ transmission line of the switch and the measured results are compared with them of conventional switch. To secure high degree of isolation, the switch with the DGS is composed of shunt-connected PIN diodes and shows insertion loss of 0.8 dB and isolation more than 50 dB at 2.3 GHz. The size of the switch is reduced about $50\%$ only with the DGS patterns while it has very similar performance to the conventional shunt-type switch.

• Journal of the Korean Ceramic Society
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• v.48 no.6
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• pp.549-558
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• 2011

Application of a generalized equivalent circuit including the electrode condition for the Hebb-Wagner polarization in the frequency domain proposed by Jamnik and Maier can provide a consistent set of material parameters, such as the geometric capacitance, partial conductivities, chemical capacitance or diffusivity, as well as electrode characteristics. Generalization of the shunt capacitors for the chemical capacitance by the constant phase elements (CPEs) was applied to a model mixed conducting system, $Ag_2S$, with electron-blocking AgI electrodes and ion-blocking Pt electrodes. While little difference resulted for the electron-blocking cell with almost ideal Warburg behavior, severely non-ideal behavior in the case of Pt electrodes not only necessitates a generalized transmission line model with shunt CPEs but also requires modelling of the leakage in the cell approximately proportional to the cell conductance, which then leads to partial conductivity values consistent with the electron-blocking case. Chemical capacitance was found to be closer to the true material property in the electron-blocking cell while excessively high chemical capacitance without expected silver activity dependence resulted in the electron-blocking cell. A chemical storage effect at internal boundaries is suggested to explain the anomalies in the respective blocking configurations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.6
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• pp.365-369
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• 2016

In this paper, we fabricated Cu/Mn alloy shunt resistor with low resistance and thermal stability for use of mobile electronic devices. We designed metal alloy composed of copper (Cu) and manganese (Mn) to embody in low resistance and low TCR which are conflict each other. Cu allows high electrical conductivity and Mn serves thermal stability in this Cu/Mn alloy system. We confirmed the elemental composition of the designed metal alloy system by using energy dispersive X-ray (EDX) analysis. We obtained low resistance below $10m{\Omega}$ and low temperature coefficient of resistance (TCR) below $100ppm/^{\circ}C$ from the designed Cu/Mn alloy resistor. And in order to minimize resistance change caused by alternative frequency on circuit, shape design of the metal alloy wire is performed by rolling process. Finally, we conclude that design of the metal alloy system was successfully done by alloying Cu and 3 wt% of Mn, and the Cu/Mn alloy resistor has low resistance and thermal stability.