• Title/Summary/Keyword: Short-circuit current

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Input Filter for Direct Matrix Converter with Stepless Current Commutation Technique (스텝리스 전류 커뮤테이션 기법이 적용된 직접형 매트릭스 컨버터를 위한 입력 필터)

  • Han, Sanghun;Kwon, Soyeon;Cho, Younghoon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.2
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    • pp.152-155
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    • 2020
  • This study proposes an input filter for a gallium-nitride-based direct matrix converter with a stepless current commutation technique. Various current commutation strategies have been adopted for reliable operation of switches. These strategies are complex to be implemented and require additional components. The stepless current commutation technique is simple to operate but causes overcurrent issues due to the occurrence of short circuit on input sources. In this study, to restrict the short circuit current, we utilized GaN devices with fast switching properties and modified the input filter. The proposed input filter was verified by experimental results of induction motor drive.

Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-l00nm Technology

  • Navakanta Bhat;Thakur, Chandrabhan-Singh
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.3
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    • pp.139-144
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    • 2003
  • We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

A Study on the Operating Characteristics of Molded Case Circuit Breakers according to Temperature Rise (온도상승에 따른 배선용 차단기의 동작특성에 관한 연구)

  • Jung, Da-Woon;Kim, Jae-Ho
    • Journal of the Korean Society of Safety
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    • v.30 no.5
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    • pp.8-13
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    • 2015
  • Molded Case Circuit Breakers (MCCBs) are typically used to provide over current protection for electrical safety caused by short circuit faults and overloads in indoor low voltage power systems. The MCCB automatically connects and disconnects loads from the electrical source when the current reaches a value and duration that will cause an excessive. However, the MCCB sometimes is not interrupted due to a malfunction, nuisance tripping, or in a fire. Ensuring electrical safety is very important in a indoor low voltage power system. This paper presents the operating characteristics of MCCBs according to a temperature rise from room temperature to 160 degrees Celsius delivered by a radiant panel heater. The ABS 54c(rated current: 30A) of the hydraulic magnetic trip type was used in the experiments. The signals of temperature, voltage, and current were measured using the high accuracy Signal Conditioning Extensions for Instrumentation (SCXI) measurement system with the LabVIEW program manufactured by National Instruments. The operating characteristics were measured as functions of current amplitude and ramp-up rate. The MCCB tripping time decreased as a result of increasing current amplitude and ramp-up rate under a temperature rise condition, because the temperature and level of the current are directly proportional to the tripping time. Additionally, an instantaneous operation was observed after 8 times of the rated current, and the MCCB began to melt a surface temperature of around 300 degrees Celsius of. The experimental results coincided well with the operating curve.

Optimized Synthetic Making Test Facilities for Estimating the Making Performance of Circuit Breaker (차단기의 투입성능 평가를 위한 최적 합성투입시험설비)

  • Suh Yoon-Taek;Kim Maeng-Hvun;Song Won-Pyo;Koh Hee-Seog;Park Seung-Jae
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.54 no.6
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    • pp.284-292
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    • 2005
  • Because all of the short-circuit testing laboratories have the limitation of test facilities, the synthetic making test methods have been used to estimate the short-circuit making performance of the ultra high-voltage circuit breaker as the alternative to direct test methods. So, KERI(Korea Eelctrotechnology Research institute) has completed the construction of the synthetic making test facilities using the low capacity step-up transformer method which fulfill the requirements specified in newly revised IEC 62271-100 Edition 1.1(2003) and have the testing capability up to 550kV, 63kA full-pole circuit breaker. The test facilities using the low capacity step-up transformer method presented in this paper are made up of the unit equipments such as HCS(High-speed Closing Switch), ITMC(Initial Transient Making Current) circuit and UP TR(low capacity step-up transformer) and have the operating range of 17.6$^{\circ}$ $\~$ 145.1$^{\circ}$ for testing the circuit breaker rated on up to 50kA and 43.1$^{\circ}$ $\~$ 119.6$^{\circ}$ for more than 50kA.

Effect of inserting resistance's magnitude on OCR trip time in a short-circuit of distribution system (배전계통 사고시 투입저항 크기가 OCR트립 시간에 미치는 영향)

  • Ahn, Jae-Min;Kim, Jae-Chul;Lim, Sung-Hun;Kim, Jin-Seok;Moon, Jong-Fil
    • Proceedings of the KIEE Conference
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    • 2007.11b
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    • pp.154-155
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    • 2007
  • Increase of fault current due to larger power demand has increased the possibility of the breakdown of the power system. To protect the power system effectively from the larger fault current, several countermeasures have been proposed. Among them, the superconducting fault current limiter (SFCL) has been expected as one of the most effective solutions. In this paper, the fault current limiter, which consists of a ideal switch as a trigger part and the limiter as the limiting part, has been applied into the distribution system. From the analysis for the fault current limiting operation of SFCL, the inserting resistance's magnitude has been confirmed to affect OCR trip time in a short-circuit of distribution system.

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Short-circuit Analysis of Solenoid and Pancake Type Bifilar Winding Magnets using BSCCO tape

  • Park Dong Keun;Ahn Min Cheol;Yang Seong Eun;Yoon Il Gu;Kim Young Jae;Ko Tae Kuk
    • Progress in Superconductivity and Cryogenics
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    • v.7 no.4
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    • pp.28-31
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    • 2005
  • To verify the feasibility of bifilar winding type superconducting fault current limiter (SFCL) using BSCCO tape, two types of magnets were fabricated and tested by short-circuit in this research. Even if the FCL using high Tc superconducting (HTS) tape has zero resistance in normal state, it needs to be wound as a bifilar winding for zero inductance. Solenoid type and pancake type bifilar winding magnets are designed and fabricated with the same length of BSCCO tape. The test system consists of AC power supply, transformer, fault switch, load and bifilar winding magnet. The applied AC voltages during fault duration, 0.1s, were from 0.5V to 20V. The test results without bifilar winding magnet were compared with those with each type magnets. The test results include voltage against magnet, transport current and generated resistance curve. Thermal stability, the recovery time, was studied from the results of two type magnets. The pancake type was the most effective to limit fault current but the solenoid type was thermally the most stable. From this research, short-circuit characteristics of the two types were obtained.

Estimation of Short Circuit Power in Static CMOS Circuits (정적 CMOS 회로의 단락 소모 전력 예측 기법)

  • Baek, Jong-Humn;Jung, Seung-Ho;Kim, Seok-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.11
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    • pp.96-104
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    • 2000
  • This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution. The proposed analytical expressions can be easily applied in such applications as power estimation even when the current expression is changed.

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Effect of Ginseng Alcohol Extract on Short-Circuit Current Across the Frog Skin (인삼 알콜 추출물이 개구리 피부를 통한 short circuit current에 미치는 영향)

  • Lee, Joong-Woo;Kim, Hee-Joong;Kang, Doo-Hee
    • The Korean Journal of Physiology
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    • v.10 no.1
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    • pp.35-40
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    • 1976
  • In an attempt to examine the effect of ginseng on sodium transport across the biological membrane, we have studied effects of ginseng alcohol extract on the short-circuit current(SCC) and the $Na^+-K^+$-activated ATPase activity in isolated frog skin preparations. 1. Ginseng alcohol extract applied to the mucosal surface of the frog skin significantly increased SCC at low concentration($1{\sim}10mg%$) but decreased SCC at higher concentration($50{\sim}250mg%$). 2. Similarly, when the drug was added to the serosal bathing medium, the SCC was stimulated at low doses($5{\sim}25mg%$) and inhibibited at high doses($50{\sim}250mg%$). 3. $Na^+-K^+$-activated ATPase activity of the frog skin epidermal homogenate was significantly inhibited by ginseng alcohol extract, the effect being proportional to the concentration of the drug in the incubation mixture. These results may suggest that a low dose of ginseng alcohol extrat enhances the transepithelial sodium transport probably by increasing the permeability of outer membrane of the transporting cell to sodium ion, whereas a high dose of drug reduces the sodium transport primarly by inhibiting $Na^+-K^+$ ATPase mediated active transport step.

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DSSCs Efficiencies of Photo Electrode Thickness and Modified Photo Electrode Surface Area (광전극 두께와 표면적 변형에 따른 DSSC의 효율 특성)

  • Kwon, Sung-Yeol;Yang, Wook;Zhou, Ze-Yuan
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.27 no.2
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    • pp.115-120
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    • 2014
  • Photo electrode is an important component for DSSC. DSSCs electrical characteristics and efficiencies fabricated with different $TiO_2$ photo electrodes thickness and modified phoro electrode surface area were studied. $11{\mu}m$ $TiO_2$ photo electrode shows a 4.956% efficiency. The highest short circuit current density was a $9.949mA/cm^2$. Efficiencies and short circuit current density increased as tape casting thickness decreased. Modified surface area of the photo electrode by needle stamp processing were studied. 200 times needle stamp processing on photo electrodes shows a highest 5.168% efficiency. Also the short circuit current density was a $10.261mA/cm^2$.

A study of coordination under short-circuit conditions between circuit-breakers (저압차단기의 차단보호협조 특성연구)

  • Oh, J.S.;Na, C.B.;Ham, G.H.
    • Proceedings of the KIEE Conference
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    • 2001.07a
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    • pp.476-478
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    • 2001
  • Coordination under short-circuit conditions is a systematic application of protective devices in the electrical power system, which, in response to a fault, will remove only a minimum amount of equipment from service. The objective is not only to minimize the equipment damage and process outage costs, but also to protect personnel from the effects of these failures. The coordination study of an electric power system consists of an organizes time-current study of all devices in series from the utilization device to the source. This study is a comparison of the time it takes the individual devices to operate when certain levels of normal or abnormal current pass through the protective devices. The objective of a coordination study is to determine the characteristics, ratings, and settings of overcurrent protective devices that will ensure that the minimum unfaulted load is interrupted when the protective devices isolate a fault or overload anywhere in the system. At the same time, the devices and settings selected should provide satisfactory protection against overloads on the equipment and interrupt short-circuit as rapidly as possible.

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