• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.15-30
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• 2004

In this paper, an analytical modeling for the dark and photo-current characteristics of a buried-gate short- channel GaAs MESFET is presented. The presented model shows that the increase of drain current under illumination is largely due to not the increase of photo-conductivity in the neutral region but the narrowing effect of the depletion layer width. The carrier density profile within the neutral region is derived from solving the carrier continuity equation one-dimensionally. In deriving the photo-generated current, we assume that the photo-current is compensated with the thermionic emission current at the gate-channel interface. Moreover, the two-dimensional Poisson's equation is solved by taking into account the drain-induced longitudinal field effect. In conclusion, the proposed model seems to provide a reasonable explanation for the dark and photo current characteristics in a unified manner.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• Journal of Korean Society of Water and Wastewater
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• v.22 no.1
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• pp.113-120
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• 2008

A large majority of clearwell must be modified with maintaining the present baffles since they were underground built with the material like concrete. Therefore it is unreasonable to apply the previous research in clearwell modification which is studied with the assumption that distance between baffles is constant. In this study, internal short-circuiting estimation method (ISEM), which has the advantage of being applied at any condition, is applied to evaluate modification of A clearwell and modify B and C clerwell which have unusual characteristics. After analyzing the hydraulic efficiency at current state, modifications, where baffles, intra basins and diffuser walls are additionally installed, are considered and evaluate using ISEM. And the effect of intra basin and diffuser wall on $T_{10}/T$ is estimated and application feasibility of ISEM is evaluated. The improvement of intra basins is almost same with that of baffles. Also, short-circuiting in effluent zone can be reduced with the same level of channel zone if intra basin is added in effluent zone. However, effect range is restricted to the next channel zone. Diffuser wall can obtain the lower ISI than minimum ISI of cases where baffles and intra basins are installed. Therefore, additional improvement of $T_{10}/T$ value can be expected after $T_{10}/T$ value converges maximum only using baffles

• Journal of Electrical Engineering and Technology
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• v.12 no.6
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.15-22
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• 2008

The bulk-planer MOSFET has a scaling limitation due to the short channel effect (SCE). The Double-Gate MOSFET (DG-MOSFET) is a next generation device for nanoscale with excellent control of SCE. The quantum effect in lateral direction is important for subthreshold characteristics when the effective channel length of DG-MOSFET is less than 10nm, Also, ballistic transport is setting important. This study shows modeling and design issues of nanoscale DG-MOSFET considering the 2D quantum effect and ballistic transport. We have optimized device characteristics of DG-MOSFET using a proper value of $t_{si}$ underlap and lateral doping gradient.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• The Journal of the Acoustical Society of Korea
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• v.27 no.3E
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• pp.69-76
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• 2008

Measurements of bubble size and distribution in the surface layer of the sea, wind speed, and variation of ocean environments were made continually over a four-day period in an experiment conducted in the South Sea of Korea during 17-20 September 2007. Theoretical background of bubble population model indicates that bubble population is a function of the depth, range and wind speed and bubble effects on sound speed shows that sound speed varies with frequency. Observational evidence exhibited that the middle size bubble population fit the model very well, however, smaller ones can not follow the model probably due to their short lifetime. Meanwhile, there is also a hysteresis effect of void fraction. Observational evidence also indicates that strong changes in sound speed are produced by the presence of swarms of micro bubbles especially from 7 kHz to 50 kHz, and calculation results are consistent with the measured data in the high frequency band, but inconsistent in the low frequency band. Based on the measurements of the sound speed and high frequency transmission configuration in the bubble layer, we present an estimation of underwater acoustic channel capacity in the bubble layer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.1-6
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• 2010

We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1764-1770
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• 2011

In this paper, the subthreshold swings for doping distribution in the channel have been analyzed in double gate MOSFET(DGMOSFET). The DGMOSFET is extensively been studying since it can lessen the short channel effects(SCEs) as next -generation nano device. The degradation of subthreshold swing(SS) known as SCEs has greatly influenced on application of digital devices, and has been analyzed for structural parameter and variation of channel doping profile in DGMOSFET. The analytical model of Poisson equation has been derived from nonuniform doping distribution for DGMOSFET. To verify potential and subthreshold swing model based on this analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and subthreshold swing for DGMOSFET has been analyzed using these models.