• Title/Summary/Keyword: Short Fault

Search Result 531, Processing Time 0.024 seconds

Deep learning-based sensor fault detection using S-Long Short Term Memory Networks

  • Li, Lili;Liu, Gang;Zhang, Liangliang;Li, Qing
    • Structural Monitoring and Maintenance
    • /
    • v.5 no.1
    • /
    • pp.51-65
    • /
    • 2018
  • A number of sensing techniques have been implemented for detecting defects in civil infrastructures instead of onsite human inspections in structural health monitoring. However, the issue of faults in sensors has not received much attention. This issue may lead to incorrect interpretation of data and false alarms. To overcome these challenges, this article presents a deep learning-based method with a new architecture of Stateful Long Short Term Memory Neural Networks (S-LSTM NN) for detecting sensor fault without going into details of the fault features. As LSTMs are capable of learning data features automatically, and the proposed method works without an accurate mathematical model. The detection of four types of sensor faults are studied in this paper. Non-stationary acceleration responses of a three-span continuous bridge when under operational conditions are studied. A deep network model is applied to the measured bridge data with estimation to detect the sensor fault. Another set of sensor output data is used to supervise the network parameters and backpropagation algorithm to fine tune the parameters to establish a deep self-coding network model. The response residuals between the true value and the predicted value of the deep S-LSTM network was statistically analyzed to determine the fault threshold of sensor. Experimental study with a cable-stayed bridge further indicated that the proposed method is robust in the detection of the sensor fault.

A Study on the TRV(SLF) of Circuit Breakers According to Install Current Limit Reactors (345kV 고장전류 저감을 위한 한류리액터 설치시 차단기 TRV(근거리 고장시) 검토)

  • Park, H.S.;Kwak, J.S.;Ju, H.J.;Ryu, H.Y.;Han, S.O.
    • Proceedings of the KIEE Conference
    • /
    • 2005.07a
    • /
    • pp.371-373
    • /
    • 2005
  • An enhancement for a transmission and substation equipment in power system make the system impedance to be lower. In principle, if the system impedance become low, system stability will be better, but the fault current become very higher. It is a very big problem for CB operating. As a fact of CB operating performance, high amplitude of the fault current may cause CB operation failure because of exceeding standard value in TRV. So we simulated TRV by using the EMTP. Generally there are two types of TRV in actual power system. One is short line fault, the other is bus terminal fault. In this paper, we simulated the TRv at short line fault as installed current limit reactors to reduce fault current in 345kV ultra-high voltage system. Short line fault is caused from single line fault in transmission line.

  • PDF

EMTDC Modeling Method of DC Reactor type Superconducting Fault Current Limiter

  • Lee, Jaedeuk;Park, Minwon;Yu, In-Keun
    • Progress in Superconductivity and Cryogenics
    • /
    • v.5 no.1
    • /
    • pp.56-59
    • /
    • 2003
  • As electric power systems grow to supply the increasing electric power demand short-circuit current tends to increase and impose a severe burden on circuit breakers and power system apparatuses. Thus, all electric equipment in a power system has to he designed to withstand the mechanical and thermal stresses of potential short-circuit currents. Among current limiting devices, Fault Current Limiter (FCL) is expected to reduce the short-circuit current. Especially, Superconducting Fault Current Limiters (SFCL) offer ideal performance: in normal operation the SFCL is in its superconducting state and has negligible impedance, in the event of a fault, the transition into the normal conducting state passively limits the current. The SFCL using high-temperature superconductors offers a positive resolution to controlling fault-current levels on utility distribution and transmission networks. This study contributes to the EMTDC based modeling and simulation method of DC Reactor type SFCL. Single and three phase faults in the utility system with DC reactor type SFCLs have been simulated using EMTDC in order to coordinate with other equipments, and the results are discussed in detail.

Research on the Influence of Inter-turn Short Circuit Fault on the Temperature Field of Permanent Magnet Synchronous Motor

  • Qiu, Hongbo;Yu, Wenfei;Tang, Bingxia;Yang, Cunxiang;Zhao, Haiyang
    • Journal of Electrical Engineering and Technology
    • /
    • v.12 no.4
    • /
    • pp.1566-1574
    • /
    • 2017
  • When the inter-turn short circuit (ITSC) fault occurs, the distortion of the magnetic field is serious. The motor loss variations of each part are obvious, and the motor temperature field is also affected. In order to obtain the influence of the ITSC fault on the motor temperature distribution, firstly, the normal and the fault finite element models of the permanent magnet synchronous motor (PMSM) were established. The magnetic density distribution and the eddy current density distribution were analyzed, and the mechanism of loss change was revealed. The effects of different forms and degrees of the fault on the loss were obtained. Based on the loss analysis, the motor temperature field calculation model was established, and the motor temperature change considering the loop current was analyzed. The influence of the fault on the motor temperature distribution was revealed. The sensitivity factors that limit the motor continuous operation were obtained. Finally, the correctness of the simulation was verified by experiments. The conclusions obtained are of great significance for the fault and high temperature demagnetization of the permanent magnet analysis.

Study on Improvement of Overcurernt Relay (OCR)'s Operation Due to Application of Superconducting Fault Current Limiter (SFCL) in Power Distribution System with a Dispersed Generation (분산전원이 도입된 배전계통에 초전도한류기 적용에 따른 과전류계전기 동작향상 연구)

  • Lim, Seung-Taek;Lim, Sung-Hun
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.66 no.2
    • /
    • pp.300-304
    • /
    • 2017
  • Due to the introduction of various types of dispersed generations (DGs) with larger capacity in a power distribution system, the short-circuit current is expected to be increased, which more requires for the effective fault current limiting methods. As one of the promising countermeasures, the superconducting fault current limiter (SFCL) has been noticed. However, the decreased fault current by SFCL affects the operation of the overcurrent relay (OCR), representative protective device in a power distribution system. In this paper, the operation of the overcurrent relay due to the application of a SFCL in a power distribution system with DG linked by its bus line was analysed through the short-circuit tests. To analyze the effect of the SFCL application in a power distribution system with DG, the experimental simulated circuits were designed and the short-circuit tests for the power distributed system assembled with the DG, the OCR and the SFCL were carried out. Through the analysis on the short-circuit tests, the application of the SFCL in a power distribution system with DG could be confirmed to be contributed to the operational improvement of overcurrent relay.

Investigation of the Estimation of Time-Varying Voltage Sags Considering the Short Circuit Contributions of Rotating Machines (회전기의 기여에 의한 시변성의 순간전압강하 예측에 관한 연구)

  • Yun Sang-Yun
    • The Transactions of the Korean Institute of Electrical Engineers A
    • /
    • v.54 no.6
    • /
    • pp.315-322
    • /
    • 2005
  • In this article, 1 would like to explore the estimation method of time-varying voltage sags in large industrial systems considering the short circuit contributions of rotating machines. For the power distribution system of KEPCO(Korea Electric Power Corporation), the magnitude of initial symmetrical short circuit current is generally not changed. However, in industrial systems which contain a number of rotating machines, the magnitude of voltage sag is generally changed from the initial to the clearing time of a fault due to the decreasing contribution of rotating machines for a fault current. The time-varying characteristics of voltage sags can be calculated using a short circuit analysis that is considered the time-varying fault currents. For this, the prediction formulations of time-varying voltage sags are proposed using a foreign standard. The proposed method contains the consideration of generator and motor effects. For the test of proposed formulations, a simple system of industrial consumer is used for the comparison conventional and proposed estimation method of voltage sag characteristics.

Balanced and Unbalanced Fault Analysis of Synchronous Generator (동기 발전기의 평형 및 불평형 고장해석)

  • Park, Cheol-Won;An, Jun-Yeong;Lee, Jong-Su;Lee, Sang-Seong;Sin, Myeong-Cheol
    • Proceedings of the KIEE Conference
    • /
    • 2006.11a
    • /
    • pp.402-404
    • /
    • 2006
  • In this paper, we simulated transient-state under fault in stator windings of synchronous generator. The fault types are line to ground fault, line to line short fault, and three phase short fault. For fault analysis of generator system, the voltage equation of a synchronous machine using the two-axis theory was used. It can be used to analyze important features of faults and to develop enhanced protection methods.

  • PDF

Efficient Equivalent Fault Collapsing Algorithm for Transistor Short Fault Testing in CMOS VLSI (CMOS VLSI에서 트랜지스터 합선 고장을 위한 효율적인 등가 고장 중첩 알고리즘)

  • 배성환
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.40 no.12
    • /
    • pp.63-71
    • /
    • 2003
  • IDDQ testing is indispensable in improving Duality and reliability of CMOS VLSI circuits. But the major problem of IDDQ testing is slow testing speed due to time-consuming IDDQ current measurement. So one requirement is to reduce the number of target faults or to make the test sets compact in fault model. In this paper, we consider equivalent fault collapsing for transistor short faults, a fault model often used in IDDQ testing and propose an efficient algorithm for reducing the number of faults that need to be considered by equivalent fault collapsing. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method.

A Study on Fault Current Calculation of ±750[V] DC Distribution Grid (±750[V] 직류배전망의 고장전류 산정에 관한 연구)

  • Lee, Kyung-Min;Park, Chul-Won
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • v.67 no.10
    • /
    • pp.1286-1291
    • /
    • 2018
  • In recent years, the proliferation of DER (distributed energy resources) is progressing rapidly. In particular, research on LVDC distribution grid with various advantages has begun. In order to commercialize this LVDC grid, direct current protection method should be established by analysis of DC faults. Recently, the development of HSCB (high-speed circuit breaker) for new ${\pm}750[V]$ LVDC grid has been researched. This paper deals with the calculation of the maximum short-circuit fault current of the HSCB as a part of the development of HSCB for the LVDC distribution grid. First, modeling using PSCAD was carried out for PV array with BESS on the Gochang Power Test Center system. Next, to calculate the rated capacity of HSCB, fault currents were calculated and the characteristics were analyzed through fault simulations. Thus, this study results can help to establish short-circuit capacity calculation of HSCB and protection plan for DC protection relay system.

Analysis on Fault Current Limiting Characteristics According to Peak Current Limiting Setting of a Flux-Lock Type SFCL with Peak Current Limiting Function (피크전류제한 설정에 따른 피크전류제한 기능을 갖는 자속구속형 초전도한류기의 고장전류제한 특성 분석)

  • Ko, Seok-Cheol
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.26 no.12
    • /
    • pp.68-73
    • /
    • 2012
  • In this paper, the fault current limiting characteristics of a flux-lock type superconducting fault current limiter (SFCL) with peak current limiting function were analyzed through its short-circuit tests. The setting condition for the peak current limiting operation was derived from its electrical equivalent circuit, which was dependent on the inductance ratio between the third coil and the first coil. Through the analysis on the short-circuit tests for the flux-lock type SFCLs with the different inductance ratio between the third coil and the first coil, the setting value for the peak current limiting operation of the flux-lock type SFCL with peak current limiting function could be confirmed to be adjusted with the variation of the inductance ratio between the third coil and the first coil.