• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.5
• /
• pp.21-28
• /
• 2007

In this paper, in order to derive the two-dimensional field effect of n-InAlAs/InGaAs HEMTs, we suggested analytical model by solving the two-dimensional Poisson's equation in both InAlAs and InGaAs regions by taking into account the longitudinal field variation, field-dependent mobility, and the continuity condition of the channel current flowing within the quantum well shaped channel. Derived expressions for long and short channel devices would be applicable to the entire operating regions in a unified manner. Simulation results show that the drain saturation current increases and the threshold voltage decreases as drain voltage increases. Compared with the conventional model, the present model may offer more reasonable explanation for the drain-induced threshold voltage roll-off, the Early effect, and the channel length modulation effect. Furthermore, it is expected that the proposed model would provide more reasonable theoretical basis for analyzing various long and short channel InAlAs/InGaAs HEMT devices.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1357-1359
• /
• 2001

0.2${\mu}m$ 이하의 최소 선폭을 가지는 소자를 구현할 때 drain induced barrier lowering (DIBL)이나 hot electron effect와 같은 short channel effect (SCE)가 나타나며 이로 인하여 소자의 신뢰성이 악화되기도 한다. 이를 개선하기 위한 방법 중 하나가 silicon selective epitaxial growth (SEG)를 이용한 elevated source/drain (ESD) 구조이다. 본 연 구에서는 silicon selective epitaxial growth를 이용하여 elevated source/drain 구조를 갖는 MOSFET 소자와 일반적인 MOSFET 구조를 갖는 소자와의 차이를 elevated source/drain의 높이 변화에 따른 전류 전압 특성을 이용하여 비교, 분석하였으며 그 결과 elevated source/drain 구조가 short channel effect를 감소시킴을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.6
• /
• pp.585-593
• /
• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.1
• /
• pp.123-128
• /
• 2014

This paper analyzed the change of subthreshold current for channel dimension of double gate(DG) MOSFET. The nano-structured DGMOSFET to reduce the short channel effect had to be preciously analyze. Poisson's equation had been used to analyze the potential distribution in channel, and Gaussian function had been used as carrier distribution. The subthreshold current had been analyzed for device parameters such as channel dimension, and projected range and standard projected deviation of Gaussian function. Since this potential model was verified in the previous papers, we used this model to analyze the subthreshold current. Resultly, we know the subthreshold current was influenced on parameters of Gaussian function and channel dimension for DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.05a
• /
• pp.753-756
• /
• 2013

This paper analyzed the change of subthreshold current for channel dimension of double gate(DG) MOSFET. The nano-structured DGMOSFET to reduce the short channel effect had to be preciously analyze. Poisson's equation had been used to analyze the potential distribution in channel, and Gaussian function had been used as carrier distribution. The subthreshold current had been analyzed for device parameters such as channel dimension, and projected range and standard projected deviation of Gaussian function. Since this potential model was verified in the previous papers, we used this model to analyze the subthreshold current. Resultly, we know the subthreshold current was influenced on parameters of Gaussian function and channel dimension for DGMOSFET.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.17 no.2
• /
• pp.438-444
• /
• 1993

The circuit board of an electronic equipment were simulated with a vertical channel which had thermal blocks protruded from one of the channel walls. A rought front plate was made of a circuit board attached with short wires to simulate the back side of a printed circuit board. Natural convection experiments were carried out to study the effects of channel space and rough front plate and to find the suitable characteristic value after the fourth row. The effect of a rough front plate was negligble. There were negligible effects of the channel space on the first and second heaters. Heat transfer coefficients after the third row decreased as the channel space decreased. Heat transfer coefficients were almost constant for larger than 20 mm channel space. A characteristic length was suggested to non-dimensionalize Nu and Ra numbers in a vertical channel with protruded heaters. A correlation was obtained using the new characteristic lengths.

• Journal of information and communication convergence engineering
• /
• v.8 no.1
• /
• pp.107-111
• /
• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.97-98
• /
• 2006

For high performance transistor in the 0.14um generation, high speed sram is using a weak region of SCE(Short Channel Effect). It causes serious SCE problem (Vth Roll-Off and Punch-Through etc). This paper shows improvement of Vth roll-off and Ion/Ioff characteristics through high concentration Pocket implant, LDD(Light Dopped Dram) and low energy Implant to reduce S/D Extension resistance. We achieve stabilized Vth and Improved transistor Ion/Ioff performance of 10%.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.193-196
• /
• 2002

This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.4
• /
• pp.917-921
• /
• 2013

This paper have analyzed the change of breakdown voltage for conduction path of double gate(DG) MOSFET. The low breakdown voltage among the short channel effects of DGMOSFET have become obstacles of device operation. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The change of breakdown voltages for conduction path have been analyzed for device parameters such as channel length, channel thickness, gate oxide thickness and doping concentration. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. Resultly, we know the breakdown voltage is greatly influenced on the change of conduction path for device parameters of DGMOSFET.