• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.9-16
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• 2011

In this paper, we propose an efficience transcoder architecture to support a simutaneous multibitrate output. First, we discuss about some architectures to realize this feature. Next, we explain the proposed architecture, it shares not only VLD-IQ but alse Q-VlD which have the same quantization step sizes each other. We anlyze the numbers of Q-VLC times per on Macroblock to the investigate an effect of sharing, and evaluate its computation complexity. The result of simulation, that complexity has an upper limit and it cn support any numbers of bitstream by about 3~6 times complexity than single output.